Hi William,
The current LTIB BSP supports driving the audio codec and will even play MP3 files.
Nice touch (sorry for pun) for wanting to have touch screen generate a sound. I may pilliage that idea and see if we can implement that too :smileywink:
Please note that the Rev D and older versions of the M5329EVB had errata for the codec. The codec part on the evb only would played/output audio and the microphone input would not work. I believe new revision of the evb will have the correct codec part number to enable audio input too.
The audio codec interfaces to the MCF5329 via SSI (I2S).
Here is code snippet for initializing the I2S interface:
/*-------------------------------------------------------------------------*/
/*!
* \brief Initializes the Audio controller.
*
* \b Purpose:
* This function is called to intialize the Audio hardware
* and prepare it for use.
*
* \param base
* The address of the Audio controller.
*
* \return True upon success, false otherwise.
*/
/*-------------------------------------------------------------------------*/
static uint32 audio_init(void)
{
uint16 temp16;
uint32 index;
/********************************/
/* Setup the SPI - control link */
/********************************/
/* QSPI does not operate in slave mode. Set to master. */
temp16 = MCF_QSPI_QMR_MSTR |
MCF_QSPI_QMR_BITS(0x000) ; // 16 bit xfers
// MCF_QSPI_QMR_CPOL | // Clock plarity
// MCF_QSPI_QMR_CPHA; // leading edge of CLK
/* Lets pick 300kHz clock for now */
temp16 |= MCF_QSPI_QMR_BAUD(133);
MCF_QSPI_QMR = temp16;
// printf("QMR: 0x%04x\n", temp16);
temp16 = MCF_QSPI_QIR_WCEF |
MCF_QSPI_QIR_SPIFE |
MCF_QSPI_QIR_ABRT |
MCF_QSPI_QIR_SPIF; // Clear interrupts
MCF_QSPI_QIR = temp16;
// printf("QIR: 0x%04x\n", temp16);
/* Enable the QSPI pins */
MCF_GPIO_PAR_QSPI = ( 0
| MCF_GPIO_PAR_QSPI_PAR_SCK(3)
| MCF_GPIO_PAR_QSPI_PAR_DOUT(3)
| MCF_GPIO_PAR_QSPI_PAR_DIN(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS0(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS1(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS2(3) );
// printf("GPIO_PAR_QSPI: 0x%04x\n", temp16);
/********************************/
/* Setup the I2S - data link */
/********************************/
/* Enable SSI clock in CCM */
MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(10); // DES changed from 40 to 4 = 12MHz MCLK
/* Issue a ColdFire SSI module reset and then enable the module for programming/initialization */
MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; //DES Disable SSI module
/* SSI module uses internal CPU clock */
MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSI_SRC;
MCF_SSI_CR =
MCF_SSI_CR_I2S(1) | // Set I2S master mode
// MCF_SSI_CR_I2S(2) | // Set I2S slave mode
MCF_SSI_CR_MCE | // Set clock out on SSI_MCLK pin
MCF_SSI_CR_SYN | // Enable synchronous mode
// MCF_SSI_CR_NET | // Enable network mode
MCF_SSI_CR_TCH; // Enable two channel mode
MCF_SSI_TCR =
// MCF_SSI_TCR_TXBIT0 | // 0=shift from msb; 1=shift from lsb - DES doesn't seem to do anything if used
MCF_SSI_TCR_TFEN0 | // TX FIFO 1 enabled
MCF_SSI_TCR_TFEN1 | // TX FIFO 0 enabled
MCF_SSI_TCR_TFDIR | // internally generated frame sync
MCF_SSI_TCR_TXDIR | // internally generated bit clock
// MCF_SSI_TCR_TSHFD | // Transmit shift; 0=msb first, 1=lsb first - DES this does make difference if used
MCF_SSI_TCR_TSCKP ; // Clock polarity: 0=clk data on rising edge; 1=clk data on falling edge
// MCF_SSI_TCR_TFSI | // Frame sync active during transmission: 0=high; 1=low
// MCF_SSI_TCR_TFSL | //Transmit frame sync length: 0=one word; 1=one bit
// MCF_SSI_TCR_TEFS; // TX early frame sync: 0=TX at first bit; 1= TX 1 bit before data
MCF_SSI_CCR = MCF_SSI_CCR_WL(7) | // 16 bit word length
MCF_SSI_CCR_DC(1) | // Frame rate divider - DES DC=1 really mean two words per frame
MCF_SSI_CCR_PM(15); // using equations in section 24.4.2.2 in MCF5329RM.pdf
// MCF_SSI_CCR_DIV2; // 0=bypass; 1=divide by 2
// MCF_SSI_CCR_PSR; // Prescaler: 0=bypass; 1=divide clk by 8
MCF_SSI_TMASK = MCF_SSI_TMASK_SSI_TMASK(0xfffffffc); //DES Transmit only on time slots 1&2
MCF_SSI_IER = 0; //DES clear/disable interrupts and DMA
MCF_SSI_CR |= MCF_SSI_CR_SSI_EN; //Enable SSI module
/* Enable the SSI pins */
MCF_GPIO_PAR_SSI = ( 0
| MCF_GPIO_PAR_SSI_PAR_MCLK
| MCF_GPIO_PAR_SSI_PAR_TXD(3)
| MCF_GPIO_PAR_SSI_PAR_RXD(3)
| MCF_GPIO_PAR_SSI_PAR_FS(3)
| MCF_GPIO_PAR_SSI_PAR_BCLK(3) );
codec_write(TLV320_RESET_REG, 0x000);
codec_write(TLV320_RESET_REG, 0x000);
codec_write(TLV320_RESET_REG, 0x000);
codec_write(TLV320_RESET_REG, 0x000);
for (index = 0; index < 1000; index++)
{
asm(nop); //DES
}
codec_write(TLV320_POWER_DOWN_CTL, 0x067); // Turn off: [CLK,OSC,ADC,MIC,LINE] Turn on:[OUT,DAC]
codec_write(TLV320_DIGITAL_IF_FMT_CTL, 0x00c); // DES Set DIN I2S, Slave...setting LRSWAP does swap right and left...so does setting LRP
codec_write(TLV320_DIGITAL_APATH_CTL, 0x001); // DES: was 0x000 Set A path...As long as DACM 0 I hear audio
codec_write(TLV320_SAMPLE_RATE_CTL, TLV320_SAMPLE_22KHZ + TLV320_Sample_USB); // Set sample rate Guess for now
codec_write(TLV320_ANALOG_APATH_CTL, 0x012); //DES (012)added this line...i.e. it wasn't here before
codec_write(TLV320_DIGITAL_IF_ACT, 0x001); // Activate Dig IF
return ERR_NO_ERROR;
} /* end init() */
Regards,
David