MCF54418 Flexbus Application question

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MCF54418 Flexbus Application question

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hnmys
Contributor I

Hi

First of all, I am a beginner. Recently encountered a problem when using Flexbus, connect FPGA.  FB_ALE output signal wrong(See Appendix,Described in the reference manual, which should be active high).

Register set(In BSP Configuration) :PAR_FBCTL = f5.(set FB_ALE),PPMLR0 = fbc2f300.(enable FB Clock).

I would like to ask whether my configuration is incorrect, please enlighten me.

Thanks!

Code in Annex

Original Attachment has been moved to: Flexbus.txt.zip

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TomE
Specialist I

I would suggest supplying a real oscilloscope capture covering multiple cycles, together with some other signals in the same capture, like the Chip Selects.

> See Appendix,Described in the reference manual


I can't find any Appendix in my MCF5118 Reference Manual. There's Chapter 45 and then the last page. You should give exact details on what diagram in which chapter of what manual you're reading.


You should be looking at "Figure 20-8. Basic Read-Bus Cycle" and the following diagrams. Better, for timing information you should not read the Reference Manual, but should refer to "Figure 11. FlexBus read timing" in "4.10 FlexBus timing specifications" in the Data Sheet.


For back-to-back Read Cycles on the Flexbus I would expect to see ALE go Active/High during the S0 clock period (when CS is Inactive/High) and then go Inactive/Low during the rest of the clock cycles, while CS is Active/Low.


In that sens the ALO and CS signals are similar, and I think you're misinterpreting the High and Low parts.


> one clock cycle of 16ns(FB_CLK:62.5MHz), but measured approximately 400ns low pulse


So you have about 25 wait states?


Tom

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hnmys
Contributor I

In addition, according to the manual, FB_ALE signal for one clock cycle of 16ns(FB_CLK:62.5MHz), but measured approximately 400ns low pulse, FB_CS signal as well.

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TomE
Specialist I

I would suggest supplying a real oscilloscope capture covering multiple cycles, together with some other signals in the same capture, like the Chip Selects.

> See Appendix,Described in the reference manual


I can't find any Appendix in my MCF5118 Reference Manual. There's Chapter 45 and then the last page. You should give exact details on what diagram in which chapter of what manual you're reading.


You should be looking at "Figure 20-8. Basic Read-Bus Cycle" and the following diagrams. Better, for timing information you should not read the Reference Manual, but should refer to "Figure 11. FlexBus read timing" in "4.10 FlexBus timing specifications" in the Data Sheet.


For back-to-back Read Cycles on the Flexbus I would expect to see ALE go Active/High during the S0 clock period (when CS is Inactive/High) and then go Inactive/Low during the rest of the clock cycles, while CS is Active/Low.


In that sens the ALO and CS signals are similar, and I think you're misinterpreting the High and Low parts.


> one clock cycle of 16ns(FB_CLK:62.5MHz), but measured approximately 400ns low pulse


So you have about 25 wait states?


Tom

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hnmys
Contributor I

Tom Evans 撰写:


So you have about 25 wait states?


Tom

Thank you for your answer, depending on your tips, I removed wait States, tested once again , I was wrong before the test, did not observe the details FB_ALE signals, the signals are as follows. In other words, my previous configuration of FLEXBUS is correct.

Thanks.TEK0009.BMP.bmp

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Wlodek_D_
Senior Contributor II

Hello,

Thank you for your post, however please consider moving it to the right community place (e.g.ColdFire/68K Microcontrollers and Processors )  to get it visible for active members.

For details please see general advice Where to post a Discussion?

Thank you for using Freescale Community.

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