MCF54415 eDMA help

[mwood]

I have a MCF54415 and have not been able to get the eDMA to operate. I probably have not configured it properly but the documentation has me confused. There are several references in the users's manual claiming that the eDMA has 64 channels. For example page 1-1 of MCF54415RM.pdf states "All MCF5441x devices operate at up to 250 MHz and include ... , a 64-channel DMA controller, ...". However page 19-2 states, "16-channel implementation". I know that some other coldfire devices use a multiplexer to map the 64 possible DMA sources to the 16 available controllers but there doesn't seem to be any DMA multiplexer identified in the documentation.

So my question is, is there a DMA multiplexer register that must be set to map a DMA request from, for example the DMA Timer, to the appropriate controller?

If there is not a multiplexer then doesn't it follow that the 64 possible DMA sources identified in table 19-6 is in error?

[angelo_d]

Hi Fang,

well thanks for interesting to this issue at least. As i mentioned in my claim, the chip is still sold and not out of end of life tables, i am buying it for prototypes actually and the cost is not that cheap, so would be nice to have a correct manual, but i understand this decisions are up to higher levels. So i am trying also to contact management too to claim for this issue and see if something happen. I mean, one "part-time" resource for the whole Coldfire branch, at least to fix documentation, would be very appreciated.

Thanks,

Regards

angelo

[miduo]

Hi, Angelo

I am quite understood your feeling on this issue. Anyway, please let me know if the Rev 3 of the manual helpful at present? And for the manual updated, it is under processing... please be patient. Thanks.

[TomE]

NXP have released a new manual for this chip as promised.

Details here:

https://community.nxp.com/thread/475565 

Tom

[TomE]

Good luck with this. I actually managed to get a badly mangled manual fixed back in 2012. That's the same date as when the eDMA chapter problem in this manual was reported.

I reported the missing pages in 2009 and it was finally fixed in 2012. But then the fixed manual wasn't released, as most of the information in it is covered in other manuals. This is the "everything about the CFV3 Core" manual, but it contains details specifically about using the Core IP module in other chips. It makes interesting reading about the ColdFire Architecture, viewed from when it was written TWENTY YEARS AGO in 1998. So it is more for someone integrating the core into a custom chip (or even for groups at Motorola/Freescale who are building specific MCF53xx chips). Details here if anyone is interested:

https://community.nxp.com/message/59948

The broken manual is still linked from the above and is available here. Read the Introduction. Grab a copy while it is still there. Compare the table on 4-24 and 4-25 to see the original problems:

http://cache.freescale.com/files/netcomm/doc/ref_manual/COLDFIRE3UM.pdf

The equivalent manual for the CFV2 core is here:

https://www.rockbox.org/wiki/pub/Main/DataSheets/COLDFIRE2UM.pdf

Tom

[miduo]

Hi, all

First really thanks for your feedback on this issue. Yes, it is as Tom mentioned, this issue had been there for 6 years. And as technical support team we had respond a couple of cases regarding the error manual. However the truth is: with the declining of ColdFire, we do not have much resource to support ColdFire parts even it still available. It is really per marketing drive.

Anyway, I had respond this issue again to the document team to see if any possibility to add some errata for the Rev 4 manual to make the error corrected.

[TomE]

> possibility to add some errata

It isn't a few lines in that chapter. It is the whole chapter. There are a lot of things wrong with it, being for a completely different chip with different peripherals and DMA assignments.

The simplest way to help your customers is to get the web site maintainers to put BOTH versions of the manual on the Product Page, together with a note saying to read the V3 eDMA chapter. Or a one page Errata saying that, and with both manuals available for download.

Tom

[angelo_d]

Hi,

just as an update, i opened a claim fore the wrong rev.4, nxp replied that due to "some reasons" the manuals cannot be fixed and updated anymore. But seems there is a chance the manual rev.3 can be set as downloadable, at least. Let's see.

Regards,

angelo

[TomE]

> But seems there is a chance the manual rev.3 can be set as downloadable, at least. Let's see.

No sign of it yet. I think it would be difficult to add both Rev 3 and Rev 4 to the Documents Page for this chip. They'd need to add an explanation that the eDMA chapter in the REV4 manual is wrong and to use the REV3 one. That would look strange.

Tom

[angelo_d]

Hi Tom,

thanks for great clarifications and the time spent on this, now at least there is a clear starting point for a driver.

Best regards,

angelo

[dominochmiel]

There is problem with documentation. Probably you have reference manual in revision 4. Correct DMA chapter is in reference manual version 3. Also chapter about dma timers is wrong in some places but right now I don't remember what was wrong. I attached revision 3 manual to my post.

Enjoy

[mwood]

Thanks Pawel. That's exactly what I needed. I eventually got started by reading docs for similar processors but I'm sure there are some differences. I still have several bugs to work out so I'll give the v3 manual a good read and hopefully I learn something. Thanks again.

[angelo_d]

Hello,

i am also interested into eDMA.

I am wondering if really rev.3 is the correct datasheet, i can't undestand why rev.4 has changed to 16 channels and different register map.

Could maybe someone in NXP confirm the right datasheed revision to use of proper eDMA info ? Thanks.

[TomE]

eDMA is also a lot slower than you'd think. Unless you need to offload the main CPU, or the main one gets bogged down in poorly written code, it can often perform the transfers easier and faster than the eDMA can. Especially on the MCF54-series CPU where the CPU is very fast.

https://community.nxp.com/message/329664

Except the access time to the peripherals is a lot slower than you'd expect:

https://community.nxp.com/message/328081

That gets worse the faster the CPU gets. On the i.MX chips, peripheral accesses take about 130us (130 clocks at 1GHz) and even the "Internal 1 to 2 clock access Static RAM" takes about the same:

https://community.nxp.com/thread/355199

I've worked on an ARM-based chip where they seriously recommend you use DMA to turn a LED on and off because it takes too long to get to the port pin otherwise!

Tom

[angelo_d]

Hi Tom,

many thanks for the very useful info's, will check them carefully, so i hope someone in NXP can confirm a correct version of the manual, so to avoid tests that may be difficult to preform.

I see eDMA is used in several Fsl/NXP SoC's.

In particular,

• mcf54415 should include the eDMA hw as from the rev.3 RM, but would really be nice if NXP can confirm it officially,
• linux is including fsl-edma.c for Vybrid and Layerscape SoCs, register set is btw a bit different from mcf54415, so this driver can't be used
• ppc and kinetis, wasn't informed they also uses eDMA, will check what variant they use,
• a good new -> imx8 uses a 16 channel eDMA that seems very similar if not equal to mcf54415, except channels are 16 and not 32 as in mcf54415. And diver is available already, it could be adapted with few changes, of course knowing precisely how the mcf54415 hw is done. 

So any other info about eDMA is welcome. I am working actually on mcf54415 and linux, with Greg (linux-m68k) has been already enabled the mmu, and i already enabled spi and my specific spi-nor flash.  Next step would be the dma, even if it seems quite hard.

[TomE]

> i hope someone in NXP can confirm a correct version of the manual, so to avoid tests that may be difficult to preform

The manual has been wrong for over 6 years now, and nothing has been done to fix it. This thread was started in 2012, and nobody from Freescale or NXP has responded to it in the 6 years since then (yet).

The errors in the REV4 manual are pretty easy to see, because:

1 - "Table 1-1. MCF5441x family configurations": "64-channel DMA Controller

2 - 1.7.33 DMA Controller: 64 fully programmable channels

3 - 19.1.2 Features: "16-channel implementation" (Rev 3 says 64)

4 - Table 19-2. eDMA Controller Memory Map: "Channel n, for n = 0 to 15"

5 - Table 19-6. DMA Request Summary for eDMA: Lists SIXTY FOUR channels.

6 - All the registers with channel numbers in them only support 0-15.

7 - The "Revision History" section doesn't list any changes at all to the eDMA chapter!

So this CPU has to have a 64-channel DMA controller because it has 64 sources.

So where did the wrong chapter come from? Searching NXP's site for "16-channel implementation that performs complex data transfers" gets matches on the KS22/KS20, KE1xF, MCF52277, MCF5208 and MCF5373. The latter one is a 16-channel implementation with 16 DMA sources. So that looks to be where parts of that chapter came from. Except "Table 19-6" came from somewhere else.

They didn't document any changes to Chapter 19 in the history, so that indicates the "Revision 3" chapter is meant to be the latest version of that chapter, but it isn't available in the current manual. Or in any Errata. Or anywhere in any data available from NXP. This Community Post is the only place to get a copy.

Tom

[TomE]

All the ColdFire manuals are created by cut-and-paste from other manuals. Sometimes that goes badly wrong. That looks to be what happened when the Rev 4 manual was created six years ago. It has never been fixed and there haven't even been any Errata for the manual released in that time, so don't expect any. They haven't made the Rev 3 manual available either - this forum post is the ONLY place to get that version from!

So the answer to your question for that time has always been to read BOTH manuals, see what makes sense, and then write some code to reverse-engineer the hardware to answer the questions that you have.

The other thing to do is to search for some sample code that someone else has written that works with the hardware. Either check the following, or just type some unique eDMA register names into Google and see what it finds.

http://elixir.free-electrons.com/linux/latest/source

eDMA is also present in some Kinetis chips and the MPC range. The chapters in those manuals may be more up to date, and may (or may not) match the eDMA implementation in the ColdFire chips.

You should also search in this forum for "eDMA" and then filter out all the PPC and Kinetis ones (the "in this group) link, and then read ALL of this one and follow some of the links in it:

https://community.nxp.com/message/501640

Tom