Hi
The data sheet specifies that the ADC clock should be between 100kHz and 5MHz. This means that 5kHz would be outside of the specified operating range.
Furthermore, the ADC clock is generated from the system clock by dividing it down using the DIV value in the (ADC) CTRL2 register. The maximum DIV value is 0x1f - giving a divide of 64 ((DIV + 1)*2). If your system clock is 32MHz (64MHz PLL) then the lowest ADC speed that you can select is 500kHz - to run the ADC slower than that it would be necessary to also run the processor (PLL) slower.
Regards
Mark
www.uTasker.com
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