I'm testing and analyzing an old project that was built within codewarrior for 7.2 arch and uTasker1.3. So I'm using uTasker ADC libraries. Viewing the adc results and de micro datasheets I have some unclear adc behaviour. I write hoping someone here could bring me some light if I missunderstanding something. The code has a single ended adc bit configured (ADC_0), loop mode and seq mode. Maybe is an uTasker issue. But I would like to have somethings about the MCU's adc cleared.
Thanks in advance.
Hello,
I have just found this information in datasheet for the single ended mode. I think Note 2 and thie following formula would bring some sense to the values I was reading:
So, 111111111111000 is the max ADC value, and 0 when Vin = VREFL (with 4096 possible states between both).
Hello,
You did not mentioned any hardware board you used. The NXP evaluation board or customer board. I am not familiar with the uTasker, however I will try to clarify the ADC itself.
First please make sure that
So you should strictly follow the above ADC spec to get an accurate/full range of ADC value, the full scale should be 4095. So back to your questions:
1. yes, 3.3v with a full scale of 4095.
2. No.
3. VREFL<VADIN<VREFH