I am a newbie for freescale StarCore DSP. Now I want to set up serial rapidIO between MSC8151 and an FPGA. I firstly want to configure serial rapidIO registers in MSC8151, and started setting up a loopback connection inside the DSP processor. But looks like it does not work as expected, DST address cannot receive any data. The following is the code. Anyone can help me fix it? Thanks!
int main()
{
UINT32 i;
INT32 bdid; // Target device id
/* configure SRIO ports */
MEM_WRITE32(RIO_P0CCSR, 0x50e00001); // Disable SRIO
MEM_WRITE32(RIO_P0ADIDCSR, 0x80010000); //alternate device id
MEM_WRITE32(RIO_P0ESCSR, 0xffffffff); // Reset status register
if(1) // loopback
MEM_WRITE32(PHY0_SRDSCR2, 0x008020c0); // enable loopback
else // back-to-back
// lane E/F transmitter equalization selection bus
MEM_WRITE32(PHY0_SRDSCR1, 0x11006630); // 1.33x relative amplitude
// disable SERDES1 SRDSCR2
MEM_CLR_BITS32(HSSI_CR1, 0x00000001);
MEM_WRITE32(RIO_P0CCSR, 0x50600001); // Enable SRIO (4x)
//---------------------------------
for(i=0;i<1024;i++)
{
*(UINT32 *)(SRC_ADDR+i) = i;
}
memset((void *)DST_ADDR, 0, 1024);
// checking that 4 lanes are synchronized and aligned
if(MEM_READ32(RIO_P0SLCSR) != 0xF0800000)
{
asm(" debug");
}
MEM_WRITE32(RIO0_BDIDCSR, 0x00FF0000); //configure as agent
MEM_WRITE32(RIO0_PGCCSR, 0x40000000); // set device as initiator (master)
// Configure Delta Outbound Address Translation Management Unit
bdid = 1 << SHIFT22;
MEM_WRITE32(RIO_P0ROWBAR1, (1<<20)|(DST_ADDR >> SHIFT12)); // +1
//MEM_WRITE32(RIO_P0ROWTAR1, (2<<20)|bdid | (DST_ADDR >> SHIFT12)); // target device id << 22
MEM_WRITE32(RIO_P0ROWTAR1, bdid | (DST_ADDR >> SHIFT12)); // target device id << 22
MEM_WRITE32(RIO_P0ROWAR1, 0x8004000f | (SWRITE << SHIFT12)); // for nread, nwrite
MEM_WRITE32(RIO_P0ROWTEAR1, 0x00000000); // large mode device id
// Configure Delta Inbound Address Translation Management Unit
// delta 1 goes to mbus 1 [by default value of RIO_P1RIWAR0 ] and delta 0 goes to mbus1 [RIO_P0RIWAR1]
MEM_WRITE32(RIO_P0RIWAR1, 0x8014400f); // all the write should go through O2M1
MEM_WRITE32(RIO_P0RIWTAR1, (DST_ADDR >> SHIFT12));
//MEM_WRITE32(RIO_P0RIWBAR1, (2<<20)|(DST_ADDR >> SHIFT12));
MEM_WRITE32(RIO_P0RIWBAR1, (DST_ADDR >> SHIFT12));
#ifdef LATE_ARBITRATION
MEM_WRITE32(GCR_GCR12, 0x000100ff); // weighted/late arbitration in RIO
#endif
//---------------------------------
// Configure O2M
MEM_WRITE32(RIO0_O2MCR, 0x01050000); // max burst size 64B
// Configure OCNDMA Address Translation Management Unit
MEM_WRITE32(RIO0_D2O_LAWBAR0, SRC_ADDR >> SHIFT12);
MEM_WRITE32(RIO0_D2O_LAWAR0, 0x80b0000f); // OCN to MBus Bridge 0
MEM_WRITE32(RIO0_D2O_LAWBAR1, (1<<20)|(DST_ADDR >> SHIFT12)); //+1
MEM_WRITE32(RIO0_D2O_LAWAR1, 0x80c0000f); // RapidIO Delta Port 0
//config channel 0
*((UINT32 *)0xFFFA8110) = 0x00040000;// source attributes
*((UINT32 *)0xFFFA8114) = SRC_ADDR;
*((UINT32 *)0xFFFA8118) = 0x40040001;// destination attributes +1
*((UINT32 *)0xFFFA811C) = DST_ADDR;
*((UINT32 *)0xFFFA8120) = 32123;
*((UINT32 *)0xFFFA8100) = 0x0f00004; //MR
asm(" debug");
*((UINT32 *)0xFFFA8100) = 0x0f00005; //enable channel 0
//*((UINT32 *)0xFFFA8180) = 0x0f00005; //enable channel 1
asm(" syncio");
MEM_WRITE32(RIO_P0SLEICR, 0xF0000001); //alert for testing, inject error *********************
for(i=0; i<1000000;i++)
{
asm(" nop");
}
asm(" debug");
