QCVS does not regenerate an imported file correctly and the LS1021ATWR does not boot

[lucroy]

I tried a simple exercise, import an existing RCW in QCVS4.4.1 and regenerate it.

Unfortunately, the new RCW is different in a few places and the target fails to boot.

Except for the checksum, the only difference is the following bytes:

005a 0421 -> 0050 0401

From what I understand, these bytes are reserved so I have no ways to know what they are doing.

Original RCW (boots at addr 0x60000000)

=> md.w 62800000

62800000: 55aa 55aa ee01 0001 0806 0a00 0000 0000    .U.U............

62800010: 0000 0000 0000 0000 0070 0000 0000 0079    ........p.....y.

62800020: 02e0 005a 0421 0060 0000 0000 0000 0000    ..Z.!.`.........

62800030: 0000 0000 0020 0000 0800 0000 1b88 4073    .... .........s@

62800040: 0000 0000 0000 0000 5709 0002 ffff ffff    .........W......

62800050: ee09 0002 1060 0000 ea09 5c08 5000 8028    ....`......\.P(.

62800060: ea09 6005 8080 0000 6108 4000 da79 e7f9    ...`.....a.@y...

62800070: ffff ffff ffff ffff ffff ffff ffff ffff    ................

Generated RCW (does not boots)

=> md.w 60000000

60000000: 55aa 55aa ee01 0001 0806 0a00 0000 0000    .U.U............

60000010: 0000 0000 0000 0000 0070 0000 0000 0079    ........p.....y.

60000020: 02e0 0050 0401 0060 0000 0000 0000 0000    ..P...`.........

60000030: 0000 0000 0020 0000 0800 0000 1b88 4073    .... .........s@

60000040: 0000 0000 0000 0000 5709 0002 ffff ffff    .........W......

60000050: ee09 0002 1060 0000 ea09 5c08 5000 8028    ....`......\.P(.

60000060: ea09 6005 8080 0000 6108 4000 3569 b238    ...`.....a.@i58.

60000070: 0000 0000 0000 0000 0000 0000 0000 0000    ................

Uboot being used:

U-Boot 2015.01+ls1+g3281947 (Jul 30 2015 - 20:01:52)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
Clock Configuration:
       CPU0(ARMV7):1000 MHz,
       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),
Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 70000000 00007900 e0025a00 21046000
       00000020: 00000000 00000000 00000000 20000000
       00000030: 00080000 881b7340 00000000 00000000
Board: LS1021ATWR
CPLD:  V2.0
PCBA:  V1.0
VBank: 0
I2C:   ready
DRAM:  1 GiB
Using SERDES1 Protocol: 112 (0x70)
Firmware 'Microcode version 0.0.1 for LS1021a r1.0' for 1021 V1.0
QE: uploading microcode 'Microcode for LS1021a r1.0' version 0.0.1
Flash: 128 MiB
MMC:   FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex no link, regs @ 0x3400000
PCIe2: Root Complex no link, regs @ 0x3500000
In:    serial
Out:   serial
Err:   serial
SEC0: RNG instantiated
SATA link 0 timeout.
AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc
scanning bus for devices...
Found 0 device(s).
SCSI:  Net:   eTSEC2 is in sgmii mode.
eTSEC1, eTSEC2, eTSEC3 [PRIME]

[mihaisurdeanu]

Hi Luc!

Thank you for reporting this issue. The fix was implemented and should be visible starting with QCVS 4.5.

Best regards,

Mihai Surdeanu

[lucroy]

When will it be available on your web site?

Right now, it still proposes to download 4.4.1.

[mihaisurdeanu · Accepted solution]

Hi Luc!

We are planning to release QCVS 4.5 in ~10 days from now.

Thank you.

[addiyi]

Unfortunately, PBL generated with QCVS will set the reserved bits to a default value (which may be wrong in some cases). We have in mind to add a new feature, to preserve the values of reserved bits to the one to imported PBL.  

Also, I have one question: Have you get this PBL from SDK or from other source?

Adrian

[lucroy]

It is what I found on the board when I received it from NXP/freescale (or from the reseller we use).

When can we expect to have a fix that you describe?

Is there an RCW that would work with QCVS and the LS1021ATWR?

[addiyi]

A fix will be provided in a future QCVS release. All RCWs from SDK should work fine with QCVS.

Adrian