Re: CodeWarrior 10.5 for Power Arch with QCVS
I'm using the DDR Configuration tool from QCVS to configure for DDR3L.
I'm trying to add config for extended temperature self-refresh (ASR/SRT). My MR2 value (SDRAM_MODE_2) is always zero. Where do I configure for self-refresh?
Also, how is DDR_SDRAM_INTERVAL calculated? My device datasheet (IS46TR16128DL) specifies a refresh interval of 8K cycles. How do I achieve this?
Thanks