MPC5566 Init EBI and SRAM

[balaji76]

Dear Sir,

    I am using Evaluation Board for testing External SRAM and configured for 0x20000000.  I can write/read data to/from SRAM after download the firmware for first time. The data is not correct after reset/power off/on the evaluation board.  The following steps are followed.

1. Create a new project code warrior.

2. Init Clock, UART and init EBI.

3. Write the data to external SRAM (0x20000000 to 0x1234)

4. Read the data after written.

5. It is working after download the object to internal flash.

6. Data is not correct after download.

Mail me if any one has answer for this.

Thanking you,

Regards

Balaji

[jorge_plascencia · Accepted solution]

Hi Balaji,

It looks like problem related to MMU settings. As you can see in reference manual in “Table 16-2. MMU Configuration for Internal Flash Boot”, the EBI is mapped to physical address 0x0000_0000 by default. Not to 0x2000_0000.

If you use debugger, the reset script sets the base address of this MMU page to 0x2000_0000. But in standalone mode it is default 0x0000_0000, so it doesn’t work.

If you want to use the EBI for external SRAM, the MMU must be reconfigured. This function will change the default settings (it changes physical address from 0x0000_0000 to 0x2000_0000):

static asm void MMUEBIIsCacheInhibited(void) {

    nofralloc

    lis    r3, 0x1002       /* Select TLB entry #, define R/W replacment control */

    mtMAS0 r3               /* Load MAS0 with 0x1002 0000 for TLB entry #2 */

    tlbre                   /* Get TLB entry # information */

    mfspr  r3, MAS2

    ori     r3, r3, 0x0008   /* set I bit (Page is cache inhibited) */

    mtMAS2 r3

    /* make sure RPN is 0x20000000 */

    mfMAS3  r3

    oris    r3, r3, 0x2000

    mtMAS3  r3    

    msync                             /* make sure we finished all memory accesses */

    tlbwe                   /* Write entry defined in MAS0 (entry 2 here) to MMU TLB */

    isync                   /* Wait for tlbwe to complete, then flush instruction buffer */

    blr

}

Regards,

[Carlos_Musich]

Hi Balaji,

I think  I am not getting what the problem is. Can you please describe what is the behavior you see and which is the expected result?

regards,

Carlos