The following is a selection of the AN3762 application note, regarding the reset loop of the blank devices:
Note that the initial contents of RAM, while undefined,
power up with remarkable consistency on a single part, but its contents can vary from part to part. For this
reason, when blank parts are powered up, they will exhibit self-asserted reset loop times ranging from a
few microseconds to a few milliseconds.
If a self asserted reset loop time is lesser than the time a sync command sequence needs to complete, the
tool will not be able to synchronize with the part and establish background communications. Due to the
variable period nature of the self asserted reset loop, it is difficult to guarantee that blank parts will have
loop times long enough to allow a sync command sequence to complete.
Due to this self asserted reset loop, programming of blank parts must be done by putting the part into active
BDM mode (thus stopping user code from running) at power up and then allowing a tool to perform a sync
sequence to establish communications with the part.
Understanding the reset behavior of the part is a key to designing a production line programming system.
When the power is initially applied to an MCU, an internal mechanism sets a “POR” status bit and
continues with the reset sequence. The RESET pin is then driven low by the MCU for a number of clock
cycles (refer to particular family manuals for the number of cycles) and is then released. The RESET pin
is then sampled to see if it is high — if so, then the reset is classified as a POR and if the BKGD pin is low,
the device enters active BDM mode. If the RESET pin is low at this point, the reset is classified as a normal
reset, and the reset vector is fetched. Note that even if an external pullup resistor is not connected to the
reset pin, there’s an internal pullup resistor that will pull the reset pin high.
For a production line programming, the RESET pin must be passively pulled high and allowed to operate
without external driving influences. The critical timing area is when the RESET pin is sampled after the
internal circuitry releases the pin from being driven low. It’s best to let the passive circuitry pull this high;
coordinating an active drive to correspond to this timing would be very difficult.
To successfully program the SG family parts in a production line environment, all issues described above
need to be addressed:
- The S08SG family uses an internally generated POR to qualify the state of the BKGD, not the rising edge of RESET.
- Blank S08 parts will tend to exhibit self asserted reset loops of variable length on initial power up that may prevent a BDM tool from using the sync command sequence to gain control over the target MCU.
- Allow the RESET line to be passively pulled up and not actively driven by the programming tool.
How to do so can be summarized in the following steps:
- Hold the BKGD pin low.
- Apply power to VDD while leaving the RESET to be passively pulled high allowing the part to enter active background mode. Do not allow any glitches or noise on the RESET line after this sequence.
- Have the programming tool perform a sync command sequence to determine the target device’s BDM operating frequency.
- Program the part.
Programming tools generally do accommodate a sync sequence type of startup. They will typically hold
the BKGD pin low, then ask the user to “cycle power to the target” and then go on to perform a sync
command sequence and establish a contact with the part.
How should I test to see if my device is in a "reset loop" or not? :smileyconfused: