S08RNA4 Internal clock setting

[Robinwithu]

Hello Everybody,

Need help regarding internal clock setting of S9S08RNA4 freescale controller

   void main(void)

    {

         DisableInterrupts;

       __RESET_WATCHDOG();     // Watchdog Timer is enabled : is having 1 Khz Internal Default clock and Default Values of  appx. msec but

                                                   // in code m gettting 9.21 msec , don't know why

        ICS_C1 = 0x04;          // internal reference clock to FLL and FLL is generating 16000 Khz  ; Ref. Freqeuncy  is set at 31250 Hz * 512 = Appx.16 Mhz

        ICS_C2 = 0x00;            // BDIV = 00, Freq is now 16Mhz

        ICS_C3 = 0x60;             //Trimmed Value of Internal System Frequency

        PORT_PTAOE = 0x0F;                                                          // Define PortA (A0-A3) all Pin As Output  ; one is Output Enabled and Zero is Output Disabled for Data Direction

        PORT_PTBOE = 0x00;

        PORT_PTBIE = 0x30;                                       //  Define PortB (B4 and B5) as Input Pin  ; one is Input Enabled and Zero is Input Disabled for Data Direction

        PORT_PTAD =  0x00;                                                             // Initialise the PORTA

        PORT_PTBD =  0x00;                                                            // Initialise The PORTB

        while(1){

            PORT_PTAD =  0x0F;

            delay(100);

            PORT_PTAD =  0x00;

            delay(100);

        }

void delay(int k) { 

      int delay ; 

      for (delay=0;delay<k;delay++); 

    }

So in above code i am having two questions

1) Why i am getting Delay Period of 130µsec 'On' and 130µsec OFF .@ 16Mhz Frequency .I am expecting  1/16Mhz= 6.25 µsec

2) Default Reset time of Watchdog is appx. 4msec but i am getting 9.18msec .

please find Ref.manual for S9S08RN4

Thank you

[Derrick · Accepted solution]

Hello Pradeep,

In the S08RNA4 the CPU is being clocked at the same rate as the bus – i.e., there is no divide-by-2.  Please refer to Figure 1-2 “System clock distribution diagram”.  The S08RN and S08Px families use a newer, lower power implementation of the CPU (HCS08 V6) which is capable of being clocked at the same frequency as the bus.

For a CPU/bus frequency of 20MHz you should not need to write to register ICS_C3 as per the following description found on page 134:

“All MCU devices are factory programmed with a trim value in a factory reserved memory location. This value is uploaded to the ICS_C3 register and ICS_C4 register during any reset initialization.”

According to the specifications in the corresponding data sheet, the factory trim value should be for 39.0625kHz.  In FEI mode this gets multiplied by 512 resulting in a CPU/bus frequency of 20MHz.  If this is not the frequency which you desire, I suggest instructing the debug tool (i.e., CodeWarrior) to measure, calculate and store a trim value.  Your code will then need to copy this into ICS_C3.

I’m not sure how you arrived at the value of 0x60 for the ICS_C3 register, but this value really can’t be fixed as it will vary from device to device.  This is why the BDM interface tool will need to calculate the appropriate trim value for the MCU which it is programming.  The result of this calculation is stored at a fixed location in Flash and your program would then copy this value into ICS_C3.

When I disassemble your delay routine I calculate that the port pins will toggle approximately every 2454 cycles.  For k <256, your delay routine calculation is 42 + (24 × k) cycles.  For a value of 100, your delay routine needs 2442 cycles:

   24: void delay (int k)

delay:

00000009 89       PSHX             ; 2

0000000A 8B       PSHH             ; 2

0000000B A7FE     AIS    #-2       ; 2

   27:   for (delay=0; delay<k; delay++);

0000000D 95       TSX              ; 2

0000000E 6F01     CLR    1,X       ; 5

00000010 7F       CLR    ,X        ; 4

00000011 2006     BRA    *+8       ; 3   abs = 0x0019

00000013 95       TSX              ; 2

00000014 6C01     INC    1,X       ; 5

00000016 2601     BNE    *+3       ; 3   abs = 0x0019

00000018 7C       INC    ,X        ; 4

00000019 9EFE03   LDHX   3,SP      ; 5

0000001C 9EF301   CPHX   1,SP      ; 6

0000001F 92F2     BGT    *-12      ; 3   abs = 0x0013

   28: }

00000021 A704     AIS    #4        ; 2

00000023 81       RTS              ; 6

Using your measurement of 130μs on and off, I calculate that your bus is actually running at about 18.9MHz and that the internal reference is being trimmed to approximately 36869kHz.

By the way, a faster way to write your delay routine would be:

void delay (int k)

{

  for (; k!=0;k--);

}

And if k <256, this would be even faster:

void delay (char k)

{

  for (; k!=0;k--);

}

Although I would prefer to use “uint8_t” and “uint16_t” instead of “char” and “int”, respectively.

For the watchdog, you do not indicate that you are changing any of its default settings.  Upon reset, the watchdog timeout value is set to 0x09C4 = 2500 and its clock source is the internal 1kHz low-power oscillator.  The accuracy of this oscillator is specified as being in the range between 670Hz and 1.25kHz.   This should result in a watchdog timeout of approximately 2.5 seconds (i.e., between 2 and 3.73 seconds).  In order to get a watchdog timeout of less than 10ms, you must be writing to the watchdog registers.  I suggest taking a look at these registers via the debugger.

Best Regards,

Derrick

[Robinwithu]

Hello Derrick,,

I debugged the code  and the Default value is not what they have mentioned in datasheet WDOG_TOVAL : 0x09C4=2500 instant of that it's WDOG_TOVAL :0x0004.

I am really sorry to say but this is the first time i am using Freescale controller and really having very bad experience with datasheet.I can't trust anymore default values also  from now on.

In this case 4msec what they mentioned as defult reset time does make sense  @ 1Khz frequency with the tolerance mentioned in datasheet.

but the problem is i am getting 9.18msec which is far more than the tolerance they have mentioned.why??

[Robinwithu]

Hello Derrick,

Thank you very much for Answer .

In the S08RNA4 the CPU is being clocked at the same rate as the bus – i.e., there is no divide-by-2.  Please refer to Figure 1-2 “System clock distribution diagram”.  The S08RN and S08Px families use a newer, lower power implementation of the CPU (HCS08 V6) which is capable of being clocked at the same frequency as the bus.

:Sorry may be i am Wrong but what  I said in a Default mode  means , If i am not changing the values of ICS_C1 , ICS_C2 and ICS_C3 register and using as it is default programmed vaules than CPU is running at Appx. 8Mhz , half of Bus clock.Also in Figure 1 as you mentioned , i can see that the CPU frequency is circa 8Mhz not 20Mhz After reset.(Bdiv = 2)

For a CPU/bus frequency of 20MHz you should not need to write to register ICS_C3 as per the following description found on page 134:

: please correct me if i am wrong to Operate my CPU at 20Mhz , I Must change the value of ICS_C1=0X04 and ICS_C2=0X00 (Default 0x20) and can i do the setting for Reference frequency  value in code worrior Run=> Run configuration=>Target Settings=> Edit=>Advance Programming Option => use custom refrence frequency =>  39.0625Khz , does it will work?

“All MCU devices are factory programmed with a trim value in a factory reserved memory location. This value is uploaded to the ICS_C3 register and ICS_C4 register during any reset initialization.”

:  Here i would like to know.on Page nr 140 the values of ICS_C1, ICS_C2 and ICS_C3 what they mentioned for 20Mhz or for 5 Mhz or for 500 Khz , How that is possible cause they are not using ICS_C2 and Writting the values only  in Trimming Register ICS_C3?

When I disassemble your delay routine I calculate that the port pins will toggle approximately every 2454 cycles.  For k <256, your delay routine calculation is 42 + (24 × k) cycles.  For a value of 100, your delay routine needs 2442 cycles:

please could you tell me in datasheet where they mentioned the formula for k<256,  42 + (24 × k) cycles ???? what is the formula to calculate delay ,if i have int or long int variable ??? 

For the watchdog, you do not indicate that you are changing any of its default settings.  Upon reset, the watchdog timeout value is set to 0x09C4 = 2500 and its clock source is the internal 1kHz low-power oscillator.  The accuracy of this oscillator is specified as being in the range between 670Hz and 1.25kHz.   This should result in a watchdog timeout of approximately 2.5 seconds (i.e., between 2 and 3.73 seconds).  In order to get a watchdog timeout of less than 10ms, you must be writing to the watchdog registers.  I suggest taking a look at these registers via the debugger.

Actually for WDT i am using it in default mode and in my code in while loop i am only switching the LED ON i.e.PORT_PTAD =  0x0F; it means that code will come out only after WDT reset from forever while loop and what i can see on my Oscilloscope is it's resetting after every 9.18msec.

Could you please see on Page 313 they mentioned "1. The default timeout value after reset is approximately 4 ms." just above the NOTE.

Best Regards,

pradeep

[iansmusical]

Hello,

Without looking at the manual you attached I'd make a guess that the bus clock is always half the cpu clock before any further divisions.

Regards,

Ian

[Robinwithu]

Hello Legg,

Off course i looked manual and i know that the bus clock is always half the cpu clock in Default mode , but the problem is i am not getting the result what i am expecting with this delay and also in manual if you see the Setting of  ICS_C2 and ICS_C3 register on page 140  it looks like their is some mistake.can you please have a look on page 140 and tell me that is that setting for 20Mhz and 5Mhz is correct? and also Watch dog timer  , why i am getting  reset after 9.2 msec (Deafult) instant of 4msec.

Thank you.

[iansmusical]

Hello,

Sorry I didn't mean to imply you hadn't read the manual. I've taken a look at page 40 and yes the register names are incorrect but the descriptions for 20MHz and 5MHz do seem to be correct. For example, take 20MHz and divide by 32 gives 500KHz. Of course, whether these values when actually written to the registers generate this frequency is perhaps questionable!?

To me there is an extra divide by 2 occurring somewhere, so while it's intended to have a 20MHz bus clock, it's actually 10MHz. Have you tried putting an oscilloscope on the LED output pins and just toggling them on and off without a delay? That way you can calculate the exact number of cycles the instruction(s) take to perform the toggle and measure it on the oscilloscope.

My experience with early Freescale documentation for MPC5xxx parts is that and I'm sorry to say Freescale, not good! I had a chip that claimed a 16MHz default internal clock which was really running at 15MHz but not explained anywhere. Perhaps there is an issue like this within the RN series!?

Regards,

Ian