HCS08GB I2C Help

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HCS08GB I2C Help

Contributor III
1. Is it true the IIC module must be disabled and then enabled for every I2C Master write sequence? I don't see this documented in the MC9S08GB/GT Data Sheet, but it's in the code of the HCS08 Peripheral Module Quick Reference (below). Indeed if I don't disable the IIC module in the function below after the first write, I don't seem to get another I2C Master write.

2. Is the time delay after the START signal in write function below for the uP operation, or the receiver's benefit?

3. I'm having intermittent operation with back to back Master write sequences. Is there a need for some time delay between sending a STOP signal and writing the next byte to the IIC data register? Signal quality appears ok on the board, but the uP sometimes just stops sending during a series of Master write sequences. I'm using the IRQ handler from the HCS08QRUG.pdf.

4. Any HCS08 IIC programming tips would be welcome!

From HCS08QRUG.pdf:

unsigned char WriteBytesI2C (unsigned char slaveAddress,unsigned char numberOfBytes){


IICC_IICEN = 0; // --- disable IIC module
IICC_IICEN = 1; // --- enable IIC module
IICC_TX = 1;
IICC_MST = 1; // Send Start Bit
for(Temp=0;Temp5;Temp++); // Small delay
ICD=slaveAddress; // Send slave address
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5 Replies

Contributor I
Maybe it can help somehow
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Contributor V
I'm reading AN3291 and it's pretty spotty in the example code department.

For starters, for a master mode example, they show the I2C init to be:
void Init_I2C (void){IIC1C_IIC1EN = 1; // Enable I2C;IIC1C_TXAK = 1; // not generate ACK by master after transfer;IIC1C_MST = 0; // Slave mode actually;IIC1F = 0x99; // Set speed to 50kHz for Bus = 18.8743MHz;// 12.5k->0x39; 50k->0x99; 100k->0x59;IIC1S_SRW = 0; // R/W bit = 0;}

Doesn't make much sense to keep the module in slave mode when trying to use it as master.  Same thing with the SRW bit.

Anyone successfully using the I2C module?

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Senior Contributor II
Hi irob,

Where are you reading this code is for master ?

This AppNote currently on the web introduces the code you wrote by:

3.1 Initialization of the IIC
The main task is to set the right speed of the SCL clock signal. These clocks are based on the bus frequency.
The next task is to set the IIC module functionality — to use or not use the interrupt service routine,
activate the IIC module, and set the slave mode. Refer to Example 1, Example 2, and Example 3.

For me, that means clearly slave, and so does the comment associated...
May you please point where the mistake is so it can be modified ?

I used I2C on S12 mainly but also on HC08.

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Contributor V
Hmm, you seem to be correct, Alban.  I guess I was inferring that all of those examples were for master mode for a couple reasons:

1) Page one discusses:
This application note summarizes the common IIC bus
states and definitions and provides an example of how to
communicate with serial EEPROMs

That seems to imply master mode.

2) The later examples of the code discuss the next steps -- write byte, read byte, etc.  In those examples, the master mode bits are all changed to master.

It's not made very clear why the module has to be initialized first in a slave mode then changed.  Does this mean it must be changed back and forth between successive byte reads/writes?

Message Edited by irob on 2007-10-18 03:29 PM
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Specialist III
Hello iRob,
My understanding of the operation of the IIC module is that, the MST control bit must be written with a 1 for the master to output a start condition, and then subsequently written with a 0 to output the stop condition.  Clearing the MST bit between transactions also allows for the possibility of multiple master operation.
For the example code given in AN3291, it doesn't appear necessary to disable and re-enable the IIC module prior to each master write sequence, nor does it appear necessary to provide a delay following a start condition.
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