Hmm, you seem to be correct, Alban. I guess I was inferring that all of those examples were for master mode for a couple reasons:
1) Page one discusses:
This application note summarizes the common IIC bus
states and definitions and provides an example of how to
communicate with serial EEPROMs
That seems to imply master mode.
2) The later examples of the code discuss the next steps -- write byte, read byte, etc. In those examples, the master mode bits are all changed to master.
It's not made very clear why the module has to be initialized first in a slave mode then changed. Does this mean it must be changed back and forth between successive byte reads/writes?
Message Edited by irob on
2007-10-18 03:29 PM