HCS08 : 9S08QG8 + RDIV

[ssinfod]

Hi,

I'm currently starting with the HCS08 family and I have a question about the ICS module. (Internal Clock Source)

After a reset, the operating mode of the ICS module is set as FLL engaged Internal (FEI).

I would like to know if I can use the RDIV bits of ICSC1 register in the FEI mode ? How does the RDIV bits works in the FEI mode ?

Is that right to say the following ? :

RDIV = 000 -> fIRC = 31.25 k Hz

RDIV = 001 -> fIRC = 32.37 k Hz

RDIV = 010 -> fIRC = 33.48 k Hz

RDIV = 011 -> fIRC = 34.60 k Hz

RDIV = 100 -> fIRC = 35.71 k Hz

RDIV = 101 -> fIRC = 36.830 k Hz

RDIV = 110 -> fIRC = 37.95 k Hz

RDIV = 111 -> fIRC = 39.0625 k Hz

Where each bit of RDIV adds : (39.0625 k - 31.25 k) / 7 = 1.11 K Hz

Note :

The definition of the RDIV from the datasheet is :

Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.

Thanks for your answer.

[bigmac]

Hello,

My understanding is that variation of RDIV would be applicable to FEE mode, where a higher frequency crystal might be used.  The RDIV value should be selected so that the resulting frequency applied to the FLL is within the range 31.25 to 39.0625 kHz.

For example, if you wish to use a 4.00 MHz crystal, the division ratio would need to be 128 (RDIV = 7).  This would produce a reference frequency of 31.25 kHz, and a bus frequency of 8 MHz, or a sub-multiple, depending on the BDIV setting.

Regards,

Mac

[fabio]

I agree with MAC.

Regarding to the range from 31.25 to 39.0625 kHz, note that it is actually trimmed using the ICSTRM register and the FTRIM bit.

The RDIV is the reference dividing factor and can be 1, 2, 4, 8, 16, 32, 64 or 128.

Best regards,

[JimDon]

I don't think you should use RDIV in this manner.
If you set it to 2, this results in a Divided ref. clock frequency is 15.625K which is not in spec.
(31.25/2). If set to 4 7.815K etc.

So it must remain at 1 in this mode.

You can use the BDIV bits in in ICSC2 to divide down the resulting 8Mhz bus clock if you want a lower clock.

If you want to experiment with these settings, use Processor Expert in Device Initialization mode.
Click on CPU. Then you can experiment with different settings. PE will tell you when you are wrong.

"If FLL is enabled (FLL mode property is set to 'Engaged' or 'Bypassed Low Power') , this frequency shall be in range of 31.25 kHz to 39.0625 kHz. This property cannot by directly modified if FLL is engaged."
(Means leave RDIV alone).



Message Edited by JimDon on 2008-02-19 10:44 AM

[Ake]

Hi,

The values in the regisers are setup at powerup to generate a fBUS clock of about 4 MHz.

Regards,

Ake