Dear Botchico,
Some comments on your code:
- The check for FLL lock appears incorrect. Are you trying to check the LOCK bit?
- The clock shouln't be programmed for /1 bus speed unless the internal clock has been trimmed first. The clock might be fast and result in an out-of-spec bus speed and lock up the chip.
Another possibility is that the BDM you are using can't handle the higher bus frequency after the clock change.
I'm too lazy to check the magic numbers in your code 
The following is the code I use to achieve the same thing I believe. You are welcome to try it an see what results you get.
typedef unsigned char U8;// Clock Trim values in Flash - dummy values overwritten by flash programmerstatic const volatile U8 NV_FTRIM_INIT @0x0000FFAE = 0xFF; // LSBstatic const volatile U8 NV_MCGTRM_INIT @0x0000FFAF = 0xFF; // MSBvoid initClock( void ) { SOPT1 = SOPT1_STOPE_MASK; // Watchdog off, STOP enabled, BKGD pin enabled
if (NV_MCGTRM_INIT != 0xFF) { // Only trim & update clock if Trim values have been programmed to Flash. // Enabling x1 clock div. on untrimmed device may be out of bus clock spec.
MCGSC = NV_FTRIM_INIT; // Trim the internal clock MCGTRM = NV_MCGTRM_INIT; // Set 16 MHz bus clock assuming 31.25 MHz trim MCGC2 = (0<<MCGC2_BDIV_BITNUM);
// BDIV=0,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0 MCGC1 = (0<<MCGC1_CLKS_BITNUM)|MCGC1_IREFS_MASK;
// CLKS=00,RDIV=0,IREFS=1,IRCLKEN=0,IREFSTEN=0
// Following only applies for S08MCGV2 (and is default anyway!) MCGT = MCGT_DRST_DRS_MASK; // MCGT_DRST_DRS=1, MCGT_DMX32=0 // Wait for FLL lock while(MCGSC_LOCK == 0) { } }}
bye
