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QorIQ T1040 DIFF_SYSCLK internal termination

Question asked by fdm on Dec 6, 2016
Latest reply on Dec 7, 2016 by fdm



According to T1040 Family Datasheet, there is an internal 100-Ohm termination at DIFF_SYSCLK input.

In my custom T1040-based board I'm observing two rather different waveforms at DIFF_SYSCLK_P pin.

The first is for my default setup - SYSCLK is not used and pulled to ground:

Scope - No Termination

The second is for reworked board where both SYSCLK and DIFF_SYSCLK are connected to the clock source:

Scope - Terminated


DIFF_SYSCLK was selected as the clock input to the chip in both cases. Clock source is CDCM6208 in LVDS mode.


Next two pictures show DIFF_SYSCLK at T1040 pins (red/green - SE, blue - Diff) simulated with HyperLynx - unterminated at the CPU end:

Sim - No Termination

... and with internal 100-Ohm termination: 

Sim - Terminated

Please confirm that SYSCLK input must be connected to the clock source in order to enable internal termination at the DIFF_SYSCLK pins.

What another negative effects might be expected if SYSCLK is not connected?





(P.S. There is the discussion of T1024 DIFF_SYSCLK termination)