QorIQ T1040 DIFF_SYSCLK internal termination

[fdm]

Hi,

According to T1040 Family Datasheet, there is an internal 100-Ohm termination at DIFF_SYSCLK input.

In my custom T1040-based board I'm observing two rather different waveforms at DIFF_SYSCLK_P pin.

The first is for my default setup - SYSCLK is not used and pulled to ground:

The second is for reworked board where both SYSCLK and DIFF_SYSCLK are connected to the clock source:

DIFF_SYSCLK was selected as the clock input to the chip in both cases. Clock source is CDCM6208 in LVDS mode.

Next two pictures show DIFF_SYSCLK at T1040 pins (red/green - SE, blue - Diff) simulated with HyperLynx - unterminated at the CPU end:

... and with internal 100-Ohm termination: 

Please confirm that SYSCLK input must be connected to the clock source in order to enable internal termination at the DIFF_SYSCLK pins.

What another negative effects might be expected if SYSCLK is not connected?

BR,

   Denis

(P.S. There is the discussion of T1024 DIFF_SYSCLK termination)

[fdm · Accepted solution]

Serguei,

These pins (cfg_eng_use) have very poor and somewhere inconsistent description through the documentation.

In particular, there's misguiding note in datasheet for all three of cfg_eng_use pins (note 21 at page 46):

"This pin should have an optional pull down resistor on board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B".

(There's the same note in T1024 DS) 

Some hours of experimentation showed that the internal termination is activated if (and only if) all conditions are met:

  1) CPU is out of POR (i.e. PORESET_B is deasserted)  or  SYSCLK is applied; ^{Обновлено}

  2) cfg_eng_use0 is pulled down;

  3) cfg_eng_use1 and cfg_eng_use2 both pulled up (not down) at the moment of PORESET_B deassertion. ^{Обновлено}

BR,

   Denis

^Новое

These pins (cfg_eng_use) must be in a valid state not only at the moment of POR deassertion, but all the time during the PORESET_B assertion!

[r8070z]

Denis,

yes, the power-up (POR) configurations pins are sampled on po-reset negation. I have known that some POR configurations must be set properly for the DIFF_SYSCLK/DIFF_SYSCLK_B termination - I’ve met already the same problem on some T1 device. But pins names I got from the QorIQ T1040, T1020 Data Sheet, Rev. 2, 06/2015. Sorry I copied IFC_WP0_B/cfg_eng_use2 instead of IFC_WE0_B/cfg_eng_use0 just by chance. However for these cfg_eng_use0/1 pins it says: “21. This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pin should have an optional pull down resistor on board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B” Now I feel it sounds a little bit vague. But I concluded that only these 2 pins has to be pull down in order to support DIFF_SYSCLK/DIFF_SYSCLK_B. So it seems the data sheet should be clarified.

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[r8070z]

Have a great day,

There are 2 configuration pins IFC_OE_B/cfg_eng_use1 and IFC_WE0_B/cfg_eng_use0. These pins should have pull down resistors on board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B. Did you pull-don these pin?

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