Reading Keypad Data Register crashes i.MX 7 SoC

[falstaff]

Hello,

Our customer discovered a kernel freeze when trying to initialize the Keypad driver in Linux. Looking a bit closer in why it exactly freezes we could pinpoint a single register read during the drivers initialization: In imx_keypad_config the driver reads the Keypad Data Register (KPDR) on which line the system freezes.

static void imx_keypad_config(struct imx_keypad *keypad)
{
         unsigned short reg_val;

         /*
          * Include enabled rows in interrupt generation (KPCR[7:0])
          * Configure keypad columns as open-drain (KPCR[15:8])
          */
         reg_val = readw(keypad->mmio_base + KPCR);
         reg_val |= keypad->rows_en_mask & 0xff; /* rows */
         reg_val |= (keypad->cols_en_mask & 0xff) << 8; /* cols */
         writew(reg_val, keypad->mmio_base + KPCR);

         /* Write 0's to KPDR[15:8] (Colums) */
         reg_val = readw(keypad->mmio_base + KPDR);<FREEZE>
         reg_val &= 0x00ff;
         writew(reg_val, keypad->mmio_base + KPDR);

We can also verify that with a simple read using U-Boot.. Other register in the same block seem to work fine:

=> md.w 0x30320004 1
30320004: 0000 ..
=> md.w 0x30320002 1
30320002: 0002 ..
=> md.w 0x30320006 1
30320006:<FREEZE>

As far as I understand there should be no limitations on when this register is readable. It is only byte or half-word addressable, and md.w is addressing it using a half-word read, so this should be a valid register access.

This is reproducible on our Colibri iMX7 modules as well as on a NXP MCIMX7SABRE Rev. C (mask 2N09P). I did not found a related errata.

Best regards,

Stefan

[igorpadykov]

Hi Stefan

usually hanging occurs due to clock absence, so one can check

if kpp clock is gated, please check CCM_CCGR170 Table 5-19. CCGR Mapping Table 

i.MX7D Reference Manual

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

Additionally RDC module can impose access restrictions.

It may be useful to check read/write with jtag.

In linux one can look at kpp imx6sl-evk.dts

linux-2.6-imx.git - Freescale i.MX Linux Tree 

Best regards
igor
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[falstaff]

Hm, I first thought of clocks, too, but checked the gate mentioned in Chapter 5, Table 5-12:

Module	Module Clock (instance.clock)	Clock Root	Module Clock Gating Enable (CCGR)
KPP	kpp.ipg_clk_s	IPG_CLK_ROOT	clk_enable_kpp (CCGR120)

So after checking CCGR120, I was convinced that clocking is fine, especially since the rest of the registers seemed to work...

Anyway, now after enabling the correct gate, CCGR170, the register at offset 6 is readable too! I guess CCGR120 in the table above is an error in the reference manual....

Thanks

Best regards,

Stefan

[markruthenbeck]

All,

Thank you for finding and pointing out the errors in the reference manual. I do want to point you to table 5-19 which is the CCGR Mapping Table, which shows CCM_CCGR_170 for the KPP module.

It appears the correct data is shown in table 5-19 and incorrect in table 5-12. I have made the corrections in our systems.

thanks again,

mark