About the behavior of the CS assertion period with the DTACK mode for EIM

[yuuki]

Dear all,

We have a question about the CS assertion period with the DTACK mode for EIM.

We use i.MX6Solo.

We set EIM as follows.

RWSC=28clk / RCSA=0clk / RSCN=3clk / DAP=0(Active H) / DAPS=0(3clk)

1clk=10ns

When DTACK signal becomes active after CS was asserted, CS assertion time is extended for waiting time of DTACK.

Is this behavior right?

Best Regards,

Yuuki

[Yuri]

Hello,

  CS assertion / negation timings are configured via the RCSA and RSCN bit fields ;

it is not affected by DTACK options.

Have a great day,
Yuri

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[yuuki]

Dear Yuri-san,

Thank you for your support.

"CS assertion / negation timings are configured via the RCSA and RSCN bit fields ;
it is not affected by DTACK options."
=>
I understood that CS assertion period should be 25clk regardless of DTACK wait time.

However, The CS assertion period becomes "25clk+DTACK wait time", not 25clk.
I do not understand the reason why CS assertion period is extended.

Would you tell me the register field which we should confirm?

May I have advice?

Best Regards,
Yuuki

[Yuri]

Hi,

is it possible to look at waveforms of both "25clk+DTACK wait time", and  "25clk" configuration ?

Regards,

Yuri.

[yuuki]

Dear Yuri-san,

Thank you for your support.

We cannot send an actual wave form to you immediately.

We want to know whether the following is right operation as a design.

"CS assertion period is extended for DTACK wait period."

Best Regards,

Yuuki

[Yuri · Accepted solution]

Hello,

as for "CS assertion period is extended for DTACK wait period" :

This is the correct operation for EIM bus

Regards,

Yuri.

[Yuri]

Hello,

I do not see explict mentions about "CS assertion period is extended for

DTACK wait period". Let me forward it to the team

Regards,

Yuri.

internal link :

CS timigs in DTACK mode.