LPDDR2 pin swapping on i.MX6DL, can or not?

[elliottyang]

Hi

I would like to use e.MCP(Kingston 08EMCP08-NL2CV100-C50) which is e.MMC 8GB + LPDDR2 8Gbit on our i.MX platform .

In order to do easy pcb routing,  can I swap data bus?

I have checked this topic :LPDDR2 pin swapping on iMx6DL  he's answer is NO, but I found another reference design which is MX6QCPULPDDR2, They do swap data bus   .I don't know who is correct.. 

Could anyone help me?

Thanks,

[igorpadykov]

Hi Elliot

answer on topic was based on http://www.jedec.org/sites/default/files/docs/JESD209-2B.pdf

and implies usage LPDDR2 memory subsystem that includes both NVM and SDRAM memories,

as mentioned in Annex B "LPDDR2-NVM Boot Procedure" :

Because LPDDR2 devices (both DRAM and NVM) assign specific

functions to the different byte lanes of the data bus and even to specific bits within the

bytes, byte and bit swapping shall be avoided.

If this is only LPDRR2 chip, as in MX6QCPULPDDR2 reference design, seems

no problem with swapping.

Best regards

igor

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[elliottyang]

Hi igor

According to your document, I saw a note from page 9:

"NOTE 2 Ordering of DQ bits shall be maintained in the system, including within the package and on the PCB. DQ byte swapping and DQ bit Swapping are not allowed in the system."

That means DQ can't be swapped, right?

So I can't do this? JUST swap DQ BYTE.

Elliott

[igorpadykov]

Hi Elliot

you are right, strictly following jedec this is prohibited.

Also it may be useful to look at

Zynq LPDDR2 DQ Swap Question - Community Forums

Best regards

igor

[elliottyang]

Hi igor

Thanks for you reply,

but the i.MX6DL can't set the DQ bus by software(uboot/kernel)?

PCB layout is so hard for implement without DQ bus changing .

Elliott

[igorpadykov]

Hi Elliot

I think if Mode Reg Read is not used, then swapping

can be used, as described on link.

~igor