I'm working on an SPWM (sine wave pulse width modulation) setup in which a block of memory is written via DMA to the CnV register of a FTM (FlexTimer Module).
I have a setup in which no DMA is used and the FTM duty cycle is updated in the main loop (very dirty). This arrangement works fine but consumes a lot of CPU cycles that I would rather use for other things. The FTM CnV buffer is written to the register when the API (https://mcuxpresso.nxp.com/api_doc/dev/974/group__ftm.html#ga08e1b1c36631d42a77a5e08d76884d8b) function
The DMA setup shows no error flags in the DMA error status register, so I'm reasonably confident that it is set up ok. However, when I connect the DMAMUX to FTM CnV channel and try to run the FTM with CnV updates via DMA the FTM duty cycle is fixed at its initialisation value.
I suspect there is an option register in the FTM that I'm not setting which tells the FTM to ask the DMA for the next CnV value and update the CnV register from the buffer when the FTM counter rolls over. I am aware of the DMA bit in the FTM CnSC register but I think there must be a hardware trigger bit that I need to either enable or have the DMA fire when it updates the buffer.
Any assistance would be much appreciated.