AnsweredAssumed Answered

iMX8M MIPI-CSI 4-lane configuration

Question asked by Krisztian Bakos on Mar 20, 2019
Latest reply on Dec 29, 2019 by peterson hou



I came across an odd behavior of the iMX8M processor's MIPI-CSI camera input.

I have an AR0330 imager, which I wrote a driver for, and is working pretty neat.


The problem is, it only works if I use it with a single MIPI-CSI lane.

The moment I try to make it work with 1+ lanes (2 or 4), the image that gets in looses all the data on every other lane except "Lane 0" (at least that's what it looks like what's happening).


In the working configuration, my .dtsi looks like the following (the relevant parts):

    csi1_bridge: csi1_bridge@30a90000 {
        compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
        reg = <0x0 0x30a90000 0x0 0x10000>;
        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DUMMY>,
            <&clk IMX8MQ_CLK_CSI1_ROOT>,
            <&clk IMX8MQ_CLK_DUMMY>;
        clock-names = "disp-axi", "csi_mclk", "disp_dcic";
        status = "disabled";


mipi_csi_1: mipi_csi1@30a70000 {
        compatible = "fsl,mxc-mipi-csi2_yav";
        reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DUMMY>,
                <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
                <&clk IMX8MQ_CLK_CSI1_ESC_DIV>,
                <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>;
        clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
                 <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>,
                 <&clk IMX8MQ_CLK_CSI1_ESC_DIV>;
        assigned-clock-rates = <133000000>, <100000000>, <66000000>;
        power-domains = <&mipi_csi1_pd>;
        csis-phy-reset = <&src 0x4c 7>;
        phy-gpr = <&gpr 0x88>;
        status = "disabled";


ar0330_mipi: ar0330_mipi@10 {
status = "okay";
compatible = "ar0330";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
clock-names = "csi_mclk";
csi_id = <0>;
rst-gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
port {
ar0330_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
&csi1_bridge {
    status = "okay";

    port {
        csi1_ep: endpoint {
            remote-endpoint = <&csi1_mipi_ep>;


&mipi_csi_1 {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    port {
        mipi1_sensor_ep: endpoint1 {
                                                         remote-endpoint = <&ar0330_mipi1_ep>;
                                                         data-lanes = <1>;
        csi1_mipi_ep: endpoint2 {
                                    remote-endpoint = <&csi1_ep>;

This gets me the image, and I can switch between RAW8 and RAW12 image format after patching the mx6s_capture.c code, with the necessary V4L2 bits and pieces and toggling     fsl,two-8bit-sensor-mode;. Everything works like a charm.


Now, when I switch the camera to 4-lane or 2-lane MIPI operation, I modify the following part of the device tree:

    port {
        mipi1_sensor_ep: endpoint1 {
                                    remote-endpoint = <&ar0330_mipi1_ep>;
                                    data-lanes = <1 2 3 4>;


And obviously, my driver's register settings towards the camera, so that end also enables the 4-lane transmission.

At this point, I would expect the interface to work, but I might be missing something.

After I deploy my new device tree, I see the target booting with the new configuration:


[ 1.710335] CSI: Registered sensor subdevice: mxc-mipi-csi2.0
[ 1.714820] mxc-mipi-csi2_yav 30a70000.mipi_csi: Remote device at /mipi_csi1@30a70000/port/endpoint1 XXX found
[ 1.723539] mxc-mipi-csi2_yav 30a70000.mipi_csi1: lanes: 4, name: mxc-mipi-csi2.0
[ 3.999571] mxc-mipi-csi2_yav 30a70000.mipi_csi: Registered sensor subdevice: ar0330 3-0010


I have verified the signals with an oscilloscope and they work as expected, so the data definitely gets up until the device's pads, but unfortunately they seem to stop right there.

Also verified if the polarities are right, but that's also fine. + is + and - is - , so at this point I'd rule out HW problems.

The PCB is simulated using CST-Studio, hence I'd also doubt signal integrity problems, more so because a single lane with the same PCB can receive 4x the datarate, so I'd expect if I have the data rate's 1/4th on the other lanes, routed extremely similarly, that must not be a problem. 


I'm not entirely sure where to go for documentation as well, because it seems like the iMX8M Reference Manual has almost zero information on the CSI interface, and there are only 1-2 replies in forums saying that this device is somewhat of a mix of the iMX7 and iMX6 interfaces, regarding MIPI and CSI (?!)


Please let me know if I'm missing any documentation or driver.

Right now I'm using Yocto with kernel 4.9.51-imx_4.9.51, but I checked and none of these drivers received any update in 4.14.78.


There seems to be this reference to an upcoming driver in the freescale .dtsi file:

compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";


fs, imx8mq-csi -> Is this something that's available somewhere or is it in the makes? Maybe that's what'll be needed for more lanes to work?


Thank you in advance for your answers!

Krisztian Bakos