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LPUART0_RxTx_IRQHandler

Question asked by Kevin Lau on Feb 13, 2019
Latest reply on Feb 15, 2019 by Kevin Lau

Hi Dear reader(s),

 

For s32k146, I have set up three UART[0,1,2] ports almost the same way except the NVIC portion (vector location).  Rx Isr was called in UART1 and UART2.  But the Rx Isr for UART0 has never been called, and yet Rx() & Tx() works perfectly. I can use Tx() and Rx() on UART0 with no problem.

 

Below codes are for UART0.

 

Any ideal?

 

Thanks,

Kevin

 

void LPUART0_PORT_init(void)
{
/*!
* Pins definitions
* ===================================================
*
* Pin number | Function
*
* Possible pin location
* PTB1 | UART0 TX Mapped to pin 10 on J4
* PTB0 | UART0 RX Mapped to pin 7 on J4
*/

PCC->PCCn[PCC_PORTC_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTC */
PORTC->PCR[3]|=PORT_PCR_MUX(4); /* Port C3: MUX = ALT4, UART0 TX */
PORTC->PCR[2]|=PORT_PCR_MUX(4); /* Port C2: MUX = ALT4, UART0 RX */

}

 

void LPUART0_NVIC_init_IRQs(void)
{
S32_NVIC->ICPR[1] = 1 << (31 % 32); /* IRQ31: clr any pending IRQ*/
S32_NVIC->ISER[1] = 1 << (31 % 32); /* IRQ31: enable IRQ */
S32_NVIC->IP[31] = 0xA; /* IRQ31: priority 10 of 0-15*/

}

void LPUART0_init(void) /* Init. summary: 9600 baud, 1 stop bit, 8 bit format, no parity */
{
PCC->PCCn[PCC_LPUART0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */

PCC->PCCn[PCC_LPUART0_INDEX] |= PCC_PCCn_PCS(2) /* Clock Src = 2 (SIRCDIV2_CLK) */
| PCC_PCCn_CGC_MASK; /* Enable clock for LPUART0 regs */

LPUART0->BAUD = LPUART_BAUD_SBR(0x34) /* Initialize for 9600 baud, 1 stop: */
|LPUART_BAUD_RXEDGIE(1) /* Enable Rx interrupt */
|LPUART_BAUD_OSR(15); /* SBR=52 (0x34): baud divisor = 8M/9600/16 = ~52 */
/* OSR=15: Over sampling ratio = 15+1=16 */
/* SBNS=0: One stop bit */
/* BOTHEDGE=0: receiver samples only on rising edge */
/* M10=0: Rx and Tx use 7 to 9 bit data characters */
/* RESYNCDIS=0: Resync during rec'd data word supported */
/* LBKDIE, RXEDGIE=0: interrupts disable */
/* TDMAE, RDMAE, TDMAE=0: DMA requests disabled */
/* MAEN1, MAEN2, MATCFG=0: Match disabled */

LPUART0->CTRL = LPUART_CTRL_RIE_MASK
|LPUART_CTRL_RE_MASK /* Bit 18 Receiver Enable*/
|LPUART_CTRL_TE_MASK; /* Bit 19 Transmitter Enable*/
/* Enable transmitter & receiver, no parity, 8 bit char: */
/* RE=1: Receiver enabled */
/* TE=1: Transmitter enabled */
/* PE,PT=0: No hw parity generation or checking */
/* M7,M,R8T9,R9T8=0: 8-bit data characters*/
/* DOZEEN=0: LPUART enabled in Doze mode */
/* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ*/
/* TxDIR=0: TxD pin is input if in single-wire mode */
/* TXINV=0: TRansmit data not inverted */
/* RWU,WAKE=0: normal operation; rcvr not in statndby */
/* IDLCFG=0: one idle character */
/* ILT=0: Idle char bit count starts after start bit */
/* SBK=0: Normal transmitter operation - no break char */
/* LOOPS,RSRC=0: no loop back */
}

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