AnsweredAssumed Answered

About Max Frequency of USDHC

Question asked by Takashi Kashiwagi on Sep 30, 2018
Latest reply on Oct 6, 2018 by Takashi Kashiwagi

Hi everyone

 

I have a question about Max Frequency of USDHC1/2_CLK_ROOT.

Q. Is USDHC1/2_CLK_ROOT up to 198MHz?(Sample code and ConfigTools do not match well)

 

 

I have using IMXRT1050-EVKB with SDK v2.4.2. And I incorporated the file system with reference to the sample project (EVKB-IMXRT1050\boards\evkbimxrt1050\fatfs_examples\fatfs_sdcard).

 

According to the sample project the clock setting of USDHC_CLK_ROOT was as follows.

 

static void BOARD_USDHCClockConfiguration(void)
{
/*configure system pll PFD2 fractional divider to 18*/
CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
/* Configure USDHC clock source and divider */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
}

 

I think that this setting PFD2PFD0 is 528MHz, and USDHC_CLK_ROOT is 528MHz (PFD2PFD0 div 1).

But , In Referrence Manual(pp690), USDHC1/2_CLK_ROOT is up to 198MHz.

In addition, the above values can not be set in ConfigTools.

 

 

 

 

I tried to some setting as follows.

  • USDHC_CLK_ROOT is 176 MHz.
    •  it can be set by configtools, but My program didn't work.
  • USDHC_CLK_ROOT is 198 MHz.
    •  it can be set, by configtools but My program didn't work.
  • USDHC_CLK_ROOT is 528 MHz.
    •  it can not be set by configtools, but My program works.
  • USDHC_CLK_ROOT is 594 MHz.
    • it can not be set by configtools, but My program works.

 

Best regards,

T.Kashiwagi

Outcomes