About Max Frequency of USDHC

[Takashi_Kashiwagi]

Hi everyone

I have a question about Max Frequency of USDHC1/2_CLK_ROOT.

Q. Is USDHC1/2_CLK_ROOT up to 198MHz?(Sample code and ConfigTools do not match well)

I have using IMXRT1050-EVKB with SDK v2.4.2. And I incorporated the file system with reference to the sample project (EVKB-IMXRT1050\boards\evkbimxrt1050\fatfs_examples\fatfs_sdcard).

According to the sample project the clock setting of USDHC_CLK_ROOT was as follows.

static void BOARD_USDHCClockConfiguration(void)

{

/*configure system pll PFD2 fractional divider to 18*/

CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);

/* Configure USDHC clock source and divider */

CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);

CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);

}

I think that this setting PFD2PFD0 is 528MHz, and USDHC_CLK_ROOT is 528MHz (PFD2PFD0 div 1).

But , In Referrence Manual(pp690), USDHC1/2_CLK_ROOT is up to 198MHz.

In addition, the above values can not be set in ConfigTools.

I tried to some setting as follows.

• USDHC_CLK_ROOT is 176 MHz.
  •  it can be set by configtools, but My program didn't work.
• USDHC_CLK_ROOT is 198 MHz.
  •  it can be set, by configtools but My program didn't work.
• USDHC_CLK_ROOT is 528 MHz.
  •  it can not be set by configtools, but My program works.
• USDHC_CLK_ROOT is 594 MHz.
  • it can not be set by configtools, but My program works.

Best regards,

T.Kashiwagi

[Takashi_Kashiwagi · Accepted solution]

Hi every one,

Sorry, the reason that SDR 104 does not work properly with IMXRT1050-EVKB was a misconfiguration of PAD.:smileycry:

About IMXRT 1050 - EVKB and IMXRT 1060 - EVK,  I confirmed that USDHC_CLK_ROOT works normally at 198 MHz.

So I will mark this comment correctly for the time being.

Measures for this question are as follows.

• Since the sample code USDHC_CLK_ROOT has become 528 MHz, it needs to be set to 198 MHz. In the following example, PLL 2 PFD 0 is set to 594 MHz and 198 MHz is input to USDHC_CLK_ROOT.

  /* Init System pfd0. */

  CLOCK_InitSysPfd(kCLOCK_Pfd0, 16);

  /* Set USDHC1_PODF. */

  CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);

  /* Set Usdhc1 clock source. */

  CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1);

• Change the definition of BOARD_SD_HOST_SUPPORT_SDR 104 _ FREQ on board.h as follows.

  #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (198000000U)

Best Regards,

T.Kashiwagi

[Takashi_Kashiwagi]

Hi every one,

I experimented with IMXRT 1060-EVK and I will write the result.

· SD_CLK == 198 MHz File Write / Read Verify Test OK！
However, we still need to modify BOARD_SD_HOST_SUPPORT_SDR 104 _ FREQ.

· I used a manufacturer's card different from the time of the experiment of IMXRT 1050-EVKB.
I will confirm next week whether this difference is affecting.

For reference, card performance during testing was as follows.

BS = 8192 [BYTE], WP=10.138389 [MB/S], RP=30.268634 [MB/S]
BS = 16384 [BYTE], WP=20.601566 [MB/S], RP=48.297513 [MB/S]
BS = 32768 [BYTE], WP=19.169942 [MB/S], RP=57.728388 [MB/S]
BS = 65536 [BYTE], WP=19.172698 [MB/S], RP=57.678443 [MB/S]

Best Regards,

T.Kashiwagi

[CarlosCasillas]

Hi Kashiwagi,

You could take a look at the following Community threads:

https://community.nxp.com/thread/485134

https://community.nxp.com/message/1062302

Hope this will be useful for you.
Best regards!
/Carlos
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[Takashi_Kashiwagi]

Hi Carlos,

Thank you for responding.

I read above Community threads. Thank you bug fix. 

But Unfortunately, the above two were about the clock output by USDHC.

USDHC_CLK_ROOT is the clock input to the USDHC module.

my question are What is the correct range of USDHC_CLK_ROOT and When using SDR 104, what is the clock of USDHC_CLK_ROOT? .

I confirmed as follows

• In Reference Manual(Chapter 18 Clock Controller Module (CCM)),  USDHC_CLK_ROOT is up tp 198MHz.
•  In sample Codes,  USDHC_CLK_ROOT is 528MHz, and working with UHS-I card
• In MCUXpresso IDE, I surely USDHC_CLK_ROOT is up tp 198MHz.
• But Only Sample codes works.

Best regards,

T.Kashiwagi

[Takashi_Kashiwagi]

Hi CarlosCasillas and lpcxpresso_support

I found a cause why USDHC does not work. It was caused by BOARD_SD_HOST_SUPPORT_SD104_FREQ and USDHC_SDClock as follows.

In board.h

#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)

In fsl_usdhc.h

uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz)

{

assert(srcClock_Hz != 0U);

assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz));

In case of USDHC_CLK_ROOT == 198MHz, It stopped at the assertion of the 2nd line of USDHC_SDClock

(Because these clocks are busClock_Hz == 200MHz and srcClock_Hz == 198MHz, assertion is correct).

Also I changed BOARD_SD_HOST_SUPPORT_SD104_FREQ to 198000000.

As a result, SD card Initializing copmpleted, But File write/Read verify Test FAILED.

After all, if the sample code is correct, USDHC_CLK_ROOT must be grater than 198 MHz.  And if I set USDHC_CLK_ROOT to 198 MHz, it seems that reading and writing of SD card becomes unstable.

I will return to the first question, 

Q. how is the correct range of USDHC_CLK_ROOT?

Best Regards,

T.Kashiwagi