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imx6sx enet2 issue

Question asked by pavansingpatil on Jul 3, 2018
Latest reply on Jul 8, 2018 by igorpadykov

Hi All,

 

We are using i.MX6SX on our custom boards and we have configured enet2 in RGMII mode and using TI DP83822 phy.  With below pinmux and device tree initialization we see issue with mdc clock. The phy is configured in 2.5 Mhz/10 Mbit  mode we see  TX and RX clk are 2.5 Mhz. The ti phy driver is enabled in the kernel.

The issue we see is on ENET2_MDC there is no clock on this line and it's always low. I doubt there is no data transmission happening on MDIO line because of mdc clock issue and mdio probed is failing to idenitify the phy.

kernel is nxp patched 4.9.11_1.0.0-ga.

 

on terminal it gives the below output.

ifconfig eth1 192.168.1.10
ifconfig: SIOCSIFFLAGS: No such device

there is no transmission on rx,tx lines.

 

&fec2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_enet2>;
    phy-mode = "rgmii";
    phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
    phy-handle = <&ethphy1>;
    phy-supply = <&reg_vref_3v3>;
    fsl,magic-packet;
    status = "okay";
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

 

        ethphy1: ethernet-phy@1 {
             reg = <1>;
        };
    };
};

pinctrl_enet2: enet2grp-1 {
                fsl,pins = <
                    MX6SX_PAD_ENET1_MDIO__ENET2_MDIO    0xa0b1  /* mdio */
                    MX6SX_PAD_ENET1_MDC__ENET2_MDC        0xa0b1    /* mdc */
                    MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
                    MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
                    MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
                    MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
                    MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
                    MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
                    MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
                    MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
                    MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
                    MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
                    MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
                    MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
                    MX6SX_PAD_ENET2_CRS__ENET2_CRS        0x3081  // CRS
                    MX6SX_PAD_ENET2_COL__ENET2_COL        0x3081  // CLO
                        MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8     0x17059 // phy reset
                    MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9    0x17059 // interupt

 

                >;

any information on this would be very helpful. Thanks.

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