We have an iMX7D rev1.3 (part number MCIMX7D5EVM10SD) with DDR3L, PMIC is a PF3000 (MC34PF3000A1). U-Boot version is v2016.05. We are experiencing a very inconsistent reset behavior, different from device to device. Test case is "reset" from the u-boot prompt.
- Some devices reset fine every time (u_boot_working_reset.txt)
- Some devices hang on reset after printing "resetting ..." (u_boot_hanging_reset.txt)
- On one device the first reset always works, but it will eventually hang on the second, third or fourth reset.
There is an errata (e10574) with three alternative options to reset the SoC.
- Option: "Hardware implementation of power-on-reset (POR) Use the pin muxing capability to route the desired WDOG_B signal to an external signal. That external signal must then be connected at the board level to an active-low power-on control (PWRON) of the PMIC."
Unfortunately we cannot use this option at this point, we have to find a software solution.
- Option: "Use SRC_A7RCR0[A7_CORE_POR_RESET0] to reset the ARM A7."
We implemented this option with a u-boot patch (resetmodes.patch) in drivers/watchdog/imx_watchdog.c, reset_cpu.
#define SRC_A7RCR0 0x004
#define CORE_POR_RESET0 (1 << 0)
printf("errata option 2\n");
setbits_le32((SRC_BASE_ADDR + SRC_A7RCR0), CORE_POR_RESET0);
This option fails on all devices, system hangs after "resetting ..."
- Option: "Use the SNVS LPCR register to turn off the system power"
#define SNVS_LPCR 0x38This does not reset the chip.
#define LPCR_DUMP_EN (1 << 5)
#define LPCR_TOP (1 << 6)
printf("errata option 3\n");
setbits_le32((SNVS_BASE_ADDR + SNVS_LPCR), LPCR_DUMP_EN);
setbits_le32((SNVS_BASE_ADDR + SNVS_LPCR), LPCR_TOP);
Any help to get a consistent SoC reset is very much appreciated. Why don't the reset options work as described in the errata?
Update: Does SNVS_PMIC_ON_REQ have to be connected to the PMIC PWRON pin for Option 3 to work correctly? This is not the case in our layout.