Q&A: How is mx6 PMIC_ON_REQ under SW control?

Document created by Yixing Kong Employee on Oct 20, 2013
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Question: How is mx6 PMIC_ON_REQ under SW control?

mx6 PMIC_ON_REQ is hooked up to the PFUZE100's PWRON and Linux and our 3.0.35bsp is used.

 

Mx6 SW control is to drive the PMIC_ON_REQ pin low.  It appears from the documentation that this pin can be controlled by either another imx6 pin OR through SW control.

 

The issue is that the reference manual is not clear on how to do this.

While doing an SR search (SR 1-877711457), it does appear the PMIC_ON_REQ is controlled by SW.

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Answer:

In latest RM version, Figure 60-3. Chip on/off state flow diagram and Table 60-3. Power mode transitions in IMX6DQRM.pdf show two ways to make PMIC_ON_REQ go low.

I'm sure in latest BSP SW method had been included.

 

It turns out the SNVS module on the mx6s/dl is different from the mx6q/d which is again different from the mx6slx.

 

The bottom line is that the requirements for the SNVS functionality came primarily from the Android market so many of the Linux use cases are not supported. SW control of the PMIC_ON_REQ pin is an example of this.

 

This means that you are correct, there only 2 ways to get PMIC_ON_REQ to power up for the mx6q/d

1 -  a low on the ON/OFF pin greater than the debounce time (750ms)

2 - a wake-up/tamper event.

 

For the mx6s/dl, there are 3 ways to get PMIC_ON_REQ to power up

1 - power-on-reset on the VSNVS  (i.e first applying VSNVS)

2 -  a low on the ON/OFF pin greater than the debounce time (750ms)

3 - a wake-up/tamper event.

 

Note, in my case, where there is an external input that actually wakes up the system, turns on the PMIC and brings up the mx6 there is only 1 way to get PMIC_ON_REQ to go back high

1 - a low on the ON/OFF pin greater than the debounce time (750ms)

As it turns out, when the VSNVS_HP section is powered (i.e VDDHIGH is applied), it gates off the wake-up timer.

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