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i.mx6 33.26MHz LVDS panel cannot display in u-boot

Question asked by Jerry Lain on Nov 14, 2017
Latest reply on Nov 28, 2017 by Jerry Lain

Hi,

I'm trying to porting a panel on i.mx6dl which is LB070WV8-SL02. Typical DCLK is 33.26MHz. I'm trying to set .pixclock to 30066, then measure LVDS1_CLK_P/LVDS1_CLK_N which output is 33.26MHz. But it only has backlight without any data, if I modify .pixclock to 22222, which output clock will be 45MHz. Then display will be normal. But from spec, frequency should between 31.95MHz~34.60MHz.

 

Because I also use 33.26MHz in kernel, and display does not have any problems. So suspect it should be uboot code problems, but don't have any ideas.

 

Try to compare below related registers in u-boot between 33MHz and 45MHz, it seems nothing special.

a. IPU related registers.

b. LDB register

c. CCM registers <-- only different are CCM_ANALOG_PLL_VIDEO_NUM and CCM_ANALOG_PLL_VIDEO because set different clock.

 

Below is panel table.

.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_lvds,
.mode = {
   .name = "LG-LB070WV8",
   .refresh = 60,
   .xres = 800,
   .yres = 480,
   .pixclock = 30066,
   .left_margin = 100,
   .right_margin = 100,
   .upper_margin = 20,
   .lower_margin = 20,
   .hsync_len = 56,
   .vsync_len = 5,
   .sync = FB_SYNC_EXT,
   .vmode = FB_VMODE_NONINTERLACED

   }

 

u-boot version is U-Boot 2015.04-gd239e2d, which does not enable PLL5 clock, so we try to enable PLL5 clock by ourselves and it seems workable.

kernel version is 3.14.52.

 

If anyone has any suggestions, that will be very helpful. Thanks in advance.

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