i.MX 6D RST_to_CKE

[sugiyamatoshihi]

Hi,

I'd like to know the clock source of counting RST_to_CKE and SDE_to_RST in MMDC module.

What clock source generate this 15.258uS cycle?

I guess source clock is 32KHz CKIL, according to reference manual description below.

If 32KHz Xtal doesn't use,  it varies the timing a lot and it cannot keep JEDEC spec.

How should that timing keep without X'tal? 

DDR3: Time from SDE enable to CKE rise. In case that DDR reset# is low, will wait until it's high and then
wait this period until rising CKE. (JEDEC value is 500 us)
LPDDR2: Idle time after first CKE assertion (JEDEC value is 200 us).
NOTE: Each cycle in this field is 15.258 us.

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Yuri,

Thank you  for the answer.

I will make a ticket for further question.

BestRegards,

Sugiyama

[Yuri]

Hello,

  The recommended configurations in the RM  and DDR programming aids are based on

precise 32.768 KHz clock input assumptions. Recommend values change when sourcing

the internal ring oscillator. In particular, use larger or max value for MDOR (RST_to_CKE to 61).

You may create request / ticket for more details.

Have a great day,
Yuri

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