In the LPC436x and LPC4370 datasheets, in section 7.3.1 "ARM Cortex-M0 coprocessor" it says:
"The M0 coprocessor resides on the same AHB multi-layer matrix as the main Cortex-M0 core."
Shouldn't this instead say:
"The M0 coprocessor resides on the same AHB multi-layer matrix as the main Cortex-M4 core."
The M0 coprocessor *IS* the main Cortex-M0 core, the main processor is the Cortex-M4 core. The "ARM Cortex-M0 subsystem" is the *other* M0 core and it is not on the main AHB matrix, it has its own bus connected to the main AHB matrix via a bridge over with the SGPIO.