I have been struggling with the SDRAM on the LPCXpresso LPC54608 board since I got the board some months ago.
All of the samples runs the CPU at less than 180 MHz, and I thought, lets speed things up
I needed to do some benchmarks so I wanted to squeeze the last out of the CPU. I then discovered that the SDRAM would fail unless I set the EMC clock divider to 3 or more (less than 60 MHz). I experimented a little with the clock and divider, and it seemed that I could get reliable 70 to 75 MHz out of the SDRAM. I set the divider at 3, and forgot more or less about it. I now have a couple of my own (test) boards running (QFP208 and BGA180), also with SDRAM. I did see the exact same behavior, I could not drive the clock for the SDRAM above approx 70 MHz before the SDRAM would fail.
To be fair, my layout on the test boards were far from ideal regarding length matching etc, but the LPCXpresso board showed the same symptoms (and that one is done correctly I assumed!). I also heard from another guy that did not have problem running the SDRAM on the LPCXpresso at 90 MHz, so something was strange...
I then read the document about SDRAM interfacing LPC18xx/43xx, and there the EMCDLYCTRL register is mentioned!!
So I began experimenting!
By adding the line:
LPC_SYSCON->EMCDLYCTRL = 0x1410; // Handles EMC clock=90 MHz !!!
I can now run both the LPCXpresso board and my own boards with SDRAM at 90 MHz without any problems (passes SDRAM tests etc).
I know a lot will say to read the documentation etc, but the thing is the EMCDLYCTRL is not mentioned in any of the (nice) samples from NXP, also not for the LPCXpresso board, so maybe it's also not obvious for others than me
So, this is just a heads-up if anyone else i experiencing this. The values I used above was only a trial and error, no warranty that this is correct or suitable, you have to measure/tweak these for your own board.
Hope it helps someone.