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Configuring GPIO input with pull-down on i.mx6ul

Question asked by Michael Magyar on Apr 24, 2017
Latest reply on Apr 5, 2018 by caglar abidin

Hi All,


I am using a Hobbitboard baseboard with a IMX6UL-PICO-EMMC (processor MCIMX6GxxVM) module. I am trying to set GPIO4_IO20 as input with the 100K pull-down enabled. I am using the morty branch of Meta-Freescale, Kernel 4.9, and the TechNexion device tree here as my base device tree.


Currently, every Device Tree value results in the pin as an input but pulled high when checked with a multimeter and in the file system. Checking the schematic, there is no pull-up resistor, so I believe this to be the action of an internal pull-up, but the register values look correct.


I am checking using cat /sys/kernel/debug/gpio and checking for the gpio-116 entry.

:~# cat /sys/kernel/debug/gpio
gpiochip3: GPIOs 96-127, parent: platform/20a8000.gpio, 20a8000.gpio:
gpio-116 (                    |gpio_420_in         ) in  hi

Checking the register using memory map, it also looks to have the correspoding value I had set in the device tree. ( script from here: )
:~# python -r 0x020E046C -n 0x1
0x20e046c:   0001b0b1

Below is the device tree fragment I am using.

&gpio4 {
    gpio_420_input {
        gpios = <20 GPIO_ACTIVE_HIGH>;
        line-name = "gpio_420_in";

&uart2 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gpio_420_input &pinctrl_uart_2_rx>;
    status = "okay";

&iomuxc {
    pinctrl_gpio_420_input: gpio420inputgrp {
        fsl,pins = <
            MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b1
    pinctrl_uart_2_rx: uart2rxgrp {
        fsl,pins = <
            MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0


Can someone please advise what is wrong with this approach? Or how to enable the pin pull-down on the i.mx6ul platform?


Thank you for any replies.


imx6ul gpio pulldown