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i.MX7: SPI transactions at 1 MHz?

Question asked by Jonah Petri on Feb 28, 2017
Latest reply on Nov 13, 2017 by Jim Kapcio

In our application, we’re using the i.MX7's SDMA controller to drive ECSPI peripherals #2 and #3, which are in turn connected to external ADCs.  This is using the linux rel_imx_4.1.15_2.0.0_ga release. We need to sample these ADCs regularly at 1 MHz x 14 bits, for a total SCLK rate of 16 MHz. I am having trouble keeping the SPI transactions (SS going low) at a regular interval. There will be occasional gaps of around 10 µs where no activity is happening on the bus. I’m assuming this is happening because the ECSPI’s TXFIFO is empty, and that the SDMA is unable to keep up.

 

If I set the sampling rate to 250 kHz, I don't see these gaps.  Any idea what bottleneck I could be hitting against?   DMA maxburst is set as per the linux SDMA driver (TX maxburst is 16, RX maxburst is 32).  Priority on both SDMA channels is set at maximum, and nothing else on the system is using SDMA.

 

Here's what I see: (magenta = SS, green = SCK, yellow = SDO). 

 

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