Hello,
On the modules listing of the i.MX7 datasheet[1], it says of the ECSPI peripherals: "Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s."
However, digging into the datasheet SPI timing (section 4.11.1.1) it says that the minimum SCLK cycle timing is actually 43 ns, which is actually only 23 Mbit/s.
This seems pretty misleading, yes? Perhaps the datasheet should be corrected to reflect that it can only achieve 52 Mbit/sec in write-only mode, and full-duplex mode is limited to 23 Mbit/s?
Or am I reading it wrong?
Solved! Go to Solution.
Hi Jonah
you are right, SPI read timing (section 4.11.1.1) says that the minimum SCLK cycle
read timing is 43 ns, which is 23 Mbit/s. For write 15ns. In sect. Module list datasheet
gives very generic overview of modules capabilities and it is necessary to check exact figures
in detailed module timing parameters.
Best regards
igor
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Igor,
While the module list in the datasheet is very generic, it is inexcusable for it to actually contain erroneous assertions about the features of the hardware. Saying "Full-duplex enhanced Synchronous Serial Interface" would be generic, while "Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s." is fraudulent.
We are very disappointed, in that it is rare to find an SPI interface that can't handle the base rate of 48 Mb/s these days. Since you can't fix your silicon, you could at least be honest about its capabilities in the documentation.
John
Hi Jonah
you are right, SPI read timing (section 4.11.1.1) says that the minimum SCLK cycle
read timing is 43 ns, which is 23 Mbit/s. For write 15ns. In sect. Module list datasheet
gives very generic overview of modules capabilities and it is necessary to check exact figures
in detailed module timing parameters.
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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