AnsweredAssumed Answered

S12XHY128 self clock and PLL

Question asked by Box Li Employee on Nov 14, 2016
Latest reply on Nov 16, 2016 by iggi



As S12XHY series, we have self clock mode: if CME=1 and SCME=1. But i test with customer board, found that if adding some interference, it seems that can make both Oscillator circuit and PLL circuit down. Means that when CM check there is unstable in Osc. and try to swtich to self clock mode, but found there is some problems for PLL and MCU goes down. So result in MCU broke dowm.


Is it possible? Thanks.

If yes. And i guess the interference goes through VDD/SS PLL. I check the RM and found that

'9.2.7 VREGEN—Optional Regulator Enable Pin
This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL
must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,
the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of VREGEN, see device specification.'

I want to supply VDD/SS PLL externally. Do you know how we can set VREGEN? Although i guess may be it shouldn't open to customer. I hope can get some clue from you. Thanks.