Martin Lorenz

LPC15xx ADC maximum sample rate

Discussion created by Martin Lorenz on Jul 18, 2016
Latest reply on Aug 3, 2016 by Carlos_Mendoza


I am just examining the ADC example code periph_adc of LPCXpresso for LPC1549 and I found a strange issue:

The example code uses

/* Setup for maximum ADC clock rate */


which uses ADC_MAX_SAMPLE_RATE=50e6, the maximum ADC conversion rate of 50MHz for the 12bit ADC as given in the manual. So far so good, but stepping through the code reveals that this call translates into:

/* Set ADC clock rate */

void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate)


    uint32_t div;


    /* Get ADC clock source to determine base ADC rate. IN sychronous mode,

       the ADC base clock comes from the system clock. In ASYNC mode, it

       comes from the ASYNC ADC clock and this function doesn't work. */

    div = Chip_Clock_GetSystemClockRate() / rate;

    if (div == 0) {

        div = 1;



    Chip_ADC_SetDivider(pADC, (uint8_t) div - 1);


and the divider is set to div=72e6/50e6=1. So actually, the ADC runs with an clock rate of 72MHz which is above the specified 50MHz maximum rate. I would have expected that the CPU clock of 72MHz is divided by 2 to get 36MHz which is below the maximum value.


Even more strange: The ADC seems to work quite well with 72MHz clock. I was sampling a 50kHz sinus signal with 72MHz/26=2.77MHz sample rate (one conversion takes 26 cycles and not 25 as given in the manual) and I got reasonable noise (on the least significant bit) and reasonable distortions/non-linearities (looking on the harmonics after FFT).


Dear NXP support, can you please state on this issue?

How safe is it to operate the ADC out of limits, as given in the example code?

Will the example code be corrected?

Or will the specification be corrected, if it is save to run the ADC with 72MHz?


Do other users have experience with operating the ADC with 72MHz clock rate?


Regards, Martin