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i.MX ECC Bits Organization within NAND

Question asked by David Beaty on Jun 27, 2016
Latest reply on Jul 11, 2016 by TomE

As I understand the i.MX536’s use of NAND it doesn’t matter if the NAND has large or small pages the i.MX family always uses 512B + 16B size pages and you need move the bad block marker to fourth section free space… But I need one more level of description… I need to know exactly how the ECC lays into the free spare area. How are the ECC bits organized within the 16B free space…?

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