Deep-sleep issue with PD0_SLEEP0_HW_ENA register

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on May 8, 2017 by sdw
Content originally posted in LPCWare by wlan8051 on Thu Aug 08 03:13:50 MST 2013
So I'm trying to put the LPC4330 to Deep-sleep.

According to the manual the first thing to do is to enable the core initiating the transition, by writing a 1 (for the M4 core) or 2 (for the M0 core) to PD0_SLEEP0_HW_ENA. Only the first two bits in this register are to be written to, since 2:31 are Reserved and "user software should not write ones to reserved bits". Truth is that configuring this usually isn't really necessary since the default value for this bit field is "1", so if you want the M4 core to initiate putting the chip to sleep you can skip this step altogether. The CMSIS library does exactly that and doesn't touch it at all.

The problem I found is that if you actually do want to write to this register, it will mess up the sleep mode you're trying to put your chip to. For me it was losing the logic states of the GPIOs after entering what was configured as Deep-sleep, this should normally happen only in Deep Power-down mode. Also the current consumption was much lower than expected.

Long story short: there's a register you never really touch if you're using the peripheral library such that if you actually DO write to(even if it means just overwriting the default after-reset value), it will mess up the sleep mode you're trying to enter. Anyone had a similar experience?