Deep-sleep issue with PD0_SLEEP0_HW_ENA register

[lpcware]

Content originally posted in LPCWare by wlan8051 on Thu Aug 08 03:13:50 MST 2013
So I'm trying to put the LPC4330 to Deep-sleep.

According to the manual the first thing to do is to enable the core initiating the transition, by writing a 1 (for the M4 core) or 2 (for the M0 core) to PD0_SLEEP0_HW_ENA. Only the first two bits in this register are to be written to, since 2:31 are Reserved and "user software should not write ones to reserved bits". Truth is that configuring this usually isn't really necessary since the default value for this bit field is "1", so if you want the M4 core to initiate putting the chip to sleep you can skip this step altogether. The CMSIS library does exactly that and doesn't touch it at all.

The problem I found is that if you actually do want to write to this register, it will mess up the sleep mode you're trying to put your chip to. For me it was losing the logic states of the GPIOs after entering what was configured as Deep-sleep, this should normally happen only in Deep Power-down mode. Also the current consumption was much lower than expected.

Long story short: there's a register you never really touch if you're using the peripheral library such that if you actually DO write to(even if it means just overwriting the default after-reset value), it will mess up the sleep mode you're trying to enter. Anyone had a similar experience?

[sdw]

I had the same problem using deep sleep mode (LPC_PMC->PD0_SLEEP0_MODE = PMC_PWR_DEEP_SLEEP_MODE):

Setting LPC_PMC->PD0_SLEEP0_HW_ENA = 0x2 seems to put the whole chip in a weird state. The GPIO state seems to be completely lost. Current consumption is unknown, as the peripherals on my board use a lot of power with the GPIOs in undefined state. As far as I have seen this happens in two cases:

• writing LPC_PMC->PD0_SLEEP0_HW_ENA=0x2 while the M0 core is not yet booted: the GPIO state is immediately lost, M4 core hangs, even if not entering a sleep at all!
• writing LPC_PMC->PD0_SLEEP0_HW_ENA=0x2 before entering sleep mode on the M0 core: the GPIO state is lost as soon as sleep mode is entered on the M0 with Chip_PMC_Set_PwrState()

Solution/workaround:

The order in which the LPC_PMC registers are set seem to be important. It looks like the PD0_SLEEP0_HW_ENA register must be set after PD0_SLEEP0_MODE, contrary to the order as described in the user manual 12.2.3. See below for a fixed version of PCM_Set_PwrState(). Note the addition at line 15:

typedef enum {
    ENA_EVENT0 = (1 << 0),
    ENA_EVENT1 = (1 << 1)
} ENA_EVENT;

void PMC_Set_PwrState(CHIP_PMC_PWR_STATE_T pwr_state, ENA_EVENT ena_event)
{
    uint32_t prev_scr = SCB->SCR;

     // Set deep sleep mode bit in core-specific System Control Register
     SCB->SCR|= 0x4;

     /* Set power state in PMC */
     LPC_PMC->PD0_SLEEP0_MODE = (uint32_t) pwr_state;
    LPC_PMC->PD0_SLEEP0_HW_ENA = (uint32_t) ena_event;

     __WFI();
    // restore deep sleep bit
     SCB->SCR = prev_scr & 0x1F;
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

So far this code works for me. To put the LPC43xx in deep sleep mode from the M0 core, call the new PMC_Set_PwrState function:

// Put the LPC43xx in deep sleep from the M0 core
PMC_Set_PwrState(PMC_PWR_DEEP_SLEEP_MODE, ENA_EVENT1)‍;‍‍

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Mon Sep 02 23:15:35 MST 2013
Hi,
Interesting observation. Let us try it - never touched this register.