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K20: FTM clock divided by 2

Question asked by Michael Heidinger on May 11, 2016
Latest reply on May 17, 2016 by Michael Heidinger

Hi,

 

I use the K22 MCU, configured the clock to 80MHz.

For configuring the clock I used USBDM default setup code.

Now, I want to check if the clock is configured right:

void FTM_EPWM(void){
    // Enable clock to TIMER FTM0
   SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK;

   // Enable clock to port pins used by FTM0, we use port C
   SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;

   // Select FTM0_CH0 and FTM0_CH1 pins
 //  SIM->SOPT8 |= (SIM_SOPT8_FTM0OCH0SRC_MASK|SIM_SOPT8_FTM0OCH1SRC_MASK);

   //Set pin to right output
   PORTC->PCR[1] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH0
   PORTC->PCR[2] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH1

   FTM0->MODE&=~(FTM_MODE_WPDIS_MASK);
   FTM0->MODE|=(FTM_MODE_FTMEN_MASK);

    /* Configure timers for edge aligned PWM High True Pulses */

//printf("FTM2_ Edge_Aligned Test 1\r\n");

    //printf("Please check the waveform, 90% Hign Ture EPWM\r\n");
    FTM0->MOD = 79;
    FTM0->CONTROLS[0].CnSC= (FTM_CnSC_MS(0b10) | FTM_CnSC_ELS(0b10));   /* No Interrupts; High True pulses on Edge Aligned PWM */
    FTM0->CONTROLS[1].CnSC= 0x28;
    FTM0->CONTROLS[0].CnV=40;  /* 90% pulse width */
    FTM0->CONTROLS[1].CnV=40;

    FTM0->SC=FTM_SC_CLKS(0b01)|FTM_SC_PS(0);     /* Edge Aligned PWM running from BUSCLK / 1 */
                                                                                          // 50% Duty Cycle
    FTM0->SC = FTM_SC_CLKS(1);
}

Now, I see a 500kHz Clock instead of a 1MHz clock. Any idea where the divide by 2 hides?

-Michael

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