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Please clarify i.MX6 UART Select Input Register dte-mode doesn't transmit chars on UART

Question asked by Marco Cavallini on May 6, 2016
Latest reply on May 16, 2016 by Marco Cavallini

Please clarify i.MX6 UART Select Input.

Datasheet chapters:

37.4.572 Select Input Register (IOMUXC_UART3_UART_RTS_B_SELECT_INPUT)

37.4.573 Select Input Register (IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT)

 

Independently from the setting of fsl,dte-mode; in the DT, so I have not enabled it and I am working in DCE mode (iMX6 default), I see the behaviour below using Kernel linux-4.5.2.

 

Case #1

-----------------------------------------------------------

MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1    // new (ALT2)

MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1    // new (ALT2)

MX6QDL_PAD_EIM_D23__UART3_CTS_B  0x1b0b1    // new (ALT2)

MX6QDL_PAD_EIM_D31__UART3_RTS_B  0x1b0b1    // new (ALT4)

root@wandboard-solo:~# ./memtool 20e0908 2

Reading 0x2 count starting at address 0x020E0908

0x020E0908:  00000002 00000001

 

Case #2

-----------------------------------------------------------

MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1    // new (ALT2)

MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1    // new (ALT2)

MX6QDL_PAD_EIM_D23__UART3_RTS_B  0x1b0b1

MX6QDL_PAD_EIM_D31__UART3_CTS_B  0x1b0b1

root@wandboard-solo:~# ./memtool 20e0908 2

Reading 0x2 count starting at address 0x020E0908

0x020E0908:  00000000 00000001

 

Case #3

-----------------------------------------------------------

MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1

MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x1b0b1

MX6QDL_PAD_EIM_D23__UART3_RTS_B  0x1b0b1

MX6QDL_PAD_EIM_D31__UART3_CTS_B  0x1b0b1

root@wandboard-solo:~# ./memtool 20e0908 2

Reading 0x2 count starting at address 0x020E0908

0x020E0908:  00000000 00000000

 

If I change the IOMUXC_UART3_UART_RTS_B_SELECT_INPUT and/or IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT registers settings there is no changes in the UART behavoiur, so in DCE mode I always get TX data from MX6QDL_PAD_EIM_D24 where a change IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT shoud result in a different MX6QDL_PAD output for the TX (or RX) signal, but this is not true.

The conclusion seems that these registers setting are completely ignored by the CPU.

Could you please explain what is happening or what is wrong?

Thank you

 

See also: https://community.freescale.com/message/642420

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