I'm developing an application with the MKL03Z where I am using an external 32.768 kHz crystal connected to PTA3/EXTAL0 and PTA4/XTAL0. I have enabled the oscillator via RTC_CR[OSCE] and waited for the oscillator startup time as specified in Sections 33.3.5 and 126.96.36.199 of the reference manual.
It appears that the OSC32KCLK is going away after a WAKEUP reset from VLLS3 and takes ~125ms to recover. During this time, any modules that use ERCLK32K (RTC and LPTMR) do not get clocks. Thus it is possible for the RTC to lose 125ms every time the system comes out of VLLS3. Additionally, the LPTMR will be delayed by at least 125ms for any configured timeout.
This 125ms period equates to 4096 cycles at 32768 Hz, which leads me to believe it is associated with the startup time of the oscillator module discussed in section 188.8.131.52 of the reference manual.
Is there a way to avoid having to wait the 4096 cycles for the oscillator to stabilize after a WAKEUP reset?
I have reproduced this behavior in the "power_manager_hal_demo_frdmkl03z" sample application for the FRDM-KL03Z board by setting SIM_SOPT1[OSC32KOUT]=01 before the while(1) loop in main. This is not quite the same as I am doing in my application, since in mine I am handling WAKEUP resets different from POR/PIN resets and am only clearing the ACKISO bit in PMC_REGSC for a WAKEUP reset.
The language in the OSC (Chapter 25) and RTC (Chapter 33) sections of the reference manual are not clear to me with regard to how I should have expected OSC32KCLK to behave through a WAKEUP reset. Section 33.1 states:
"RTC_CR[OSCE] can override the configuration of the System OSC, configuring the
OSC for 32 kHz crystal operation in all power modes except VLLS0, and through any
Additionally, Section 25.1 states:
"RTC_CR[OSCE] has overriding control over the MCG_Lite and OSC_CR enable
functions. When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low
power and RTC_CR[SCxP] override OSC_CR[SCxP] to control the internal capacitance
configuration. See the RTC chapter for more details."
However, Section 25.11 (Low power modes operation) says:
"After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are
reset and initialization is required through software."
So, Section 25.11 and 33.1 seem to be at odds in terms of the reset behavior of the oscillator.