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How does “CPSID” (used to control interrupts) work?

Question asked by Rick Stuart on Apr 21, 2016
Latest reply on Apr 22, 2016 by EARL GOODRICH

How is it that “CPSID” (used in example programs to control interrupts) not show up in the processor's register set (maybe it’s under a different name?) nor is IAR able to find a definition for it (so backwards engineering is not an option).


Specifically, I want to know if executing:


__asm("CPSID i");

// ...some code which needs to be protected from interrupts...

__asm("CPSIE i");


...inside a routine will (possibly) allow the original type of interrupt to (prematurely) interrupt the code again before the code is finished servicing the first interrupt.


Added later...

So, the explanations for CPS ID & IE are not in the freescale / NXP chip specifications but the ARM specifications.  Also, these are some sort of special registers (PRIMASK and FAULTMASK) that are not in ordinary memory space?  Going on, they are 32 bit registers all of which, with the exception of the least significant bit (LSB) are reserved!


So, my question now boils down to this:


I would like to protect my code by setting the PRIMASK LSB (i.e. by using: __asm("CPSID i");) inhibiting all priority-adjustable-interrupts.  When I later clear the PRIMASK LSB (i.e. by using: __asm("CPSIE i");) enabling all priority-adjustable-interrupts, do I in fact alter any other interrupt settings or states?  For example, am I allowing the current interrupt to become active again starting an endless sequence of calls into the interrupt code I am now in?  Or, is setting and clearing the LSB in the PRIMASK more like putting in and taking out a 2nd dam on a river (i.e. the 1st dam remains intact and its function does not change throughout the construction and destruction of the 2nd dam).