Where is it described how KL17 inhibits interrupts while in an interrupt?

[rickstuart]

I ask because we are debating how interrupts work on a KL17.  Obviously an interrupt which vectors to the appropriate interrupt routine is somehow inhibited by processor hardware to repeat the process.   Otherwise an interrupt would endlessly vector to the interrupt handler until the stack blows up.   I believe this processor hardware inhibiting is active until the interrupt routine is returned from.  I would be very grateful if someone could point out where this is actually described in the KL17 documentation.

[dereksnell]

Hi Rick

The KL17 is built on the Cortex-M0+ core. And all the Cortex-M cores use the Nested Vector Interrupt Controller (NVIC) to manage Interrupt sources and priorities. The NVIC is documented in ARM's core documentation found below

And I also see Earl has already provided you a detailed description at your other post

Will the KL17 allow higher priority interrupts to interrupt a lower priority interrupt?

M0+ User Guide

http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf

Thanks