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Clock output at the SS switch of ECSPI of i.MX6Solo

Question asked by yuuki on Mar 3, 2016
Latest reply on Apr 19, 2016 by alejandrolozano

Dear all,


We connect three devices to ECSPI1 port.

We use fsl-yocto-3.10.53-1 .1.0.

The ECSPI driver remains a default.


When ECSPI1 is switched from SS1(Device2) to SS0(Device1), a clock is output momentarily just before SS0 becomes active.


Why is a clock output?




The field setting of each register is the following



- CHANNEL MODE:1 (all master mode)

- SMC: 0



- SCLK_CTL:1 (stay high)

- DATA CTL:0 (stay high)

- SS_POL:0 (Active Low)

- SS_CTL:1 (Negate Chip Select (SS) signal between SPI bursts)

- SCLK_POL:1 (Active low polarity)

- SCLK_PHA:1 (Phase 1 operation)


May I have advice?


Best Regards,