We connect three devices to ECSPI1 port.
We use fsl-yocto-3.10.53-1 .1.0.
The ECSPI driver remains a default.
When ECSPI1 is switched from SS1(Device2) to SS0(Device1), a clock is output momentarily just before SS0 becomes active.
Why is a clock output?
The field setting of each register is the following
- CHANNEL MODE:1 (all master mode)
- SMC: 0
- SCLK_CTL:1 (stay high)
- DATA CTL:0 (stay high)
- SS_POL:0 (Active Low)
- SS_CTL:1 (Negate Chip Select (SS) signal between SPI bursts)
- SCLK_POL:1 (Active low polarity)
- SCLK_PHA:1 (Phase 1 operation)
May I have advice?