Hi community,

I have a question about i.MX6 DDR3 caliblation (ddr_stress_tester_v2.40).

I'd like to calculate the actual delay of

DG_DL_ABS_OFFSET0,WL_DL_ABS_OFFSET0,RD_DL_ABS_OFFSET0 and WR_DL_ABS_OFFSET0.

So,I used ddr_stress_tester_uboot_v2.40 with our custom mx6Q board.

And,I got the following result.

****result****

WL_DL_ABS_OFFSET0:0x23

DG_DL_ABS_OFFSET0:0x334

RD_DL_ABS_OFFSET0:0x5A

WR_DL_ABS_OFFSET0:0x34

************

While,

ARM core speed :1GHz (1.0ns)

DDR_CLK frequency: 528MHz (1.894ns)

When I calculate the value of DG_DL_ABS_OFFSET0 etc. ,

which value should I choose out of 1GHz,528MHz or other frequency ?

According to *"i.MX 6Dual/6Quad Applications Processor Reference Manual,

Rev. 2, 06/2014"(***page 3977).**

The following sentence exists.

"The delay of the delay-line would be (DG_DL_ABS_OFFSET0 / 256)* MMDC_CH0

AXI clock (fast clock)."

What is the value of "MMDC_CH0 AXI clock(fast clock) " ?

I think it is 528MHz.

Is this correct or not ?

Likewise,what is the value of "clock period" of "WL_DL_ABS_OFFSET0" ?

Best Regards,

Seiichi Nakano

Hello,

Yes, by default it is 528 Mhz. Please use Figure 18-2 ( Clock Tree - Part 1)

of the i.MX6 RM regarding MMDC_CH0_CLK_ROOT and MMDC_CH1_CLK_ROOT.

Have a great day,

Yuri

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