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i.MX6 DDR3 calibration: How to calculate the value of DG_DL_ABS_OFFSET0 etc.

Question asked by SEIICHI NAKANO on Feb 15, 2016
Latest reply on Mar 1, 2016 by SEIICHI NAKANO

Hi community,

I have a question about i.MX6 DDR3 caliblation (ddr_stress_tester_v2.40).


I'd like to calculate the actual delay of DG_DL_ABS_OFFSET0,WL_DL_ABS_OFFSET0,RD_DL_ABS_OFFSET0 and WR_DL_ABS_OFFSET0.

So,I used ddr_stress_tester_uboot_v2.40 with our custom mx6Q board.
And,I got the following result.



ARM core speed :1GHz      (1.0ns)
DDR_CLK frequency: 528MHz (1.894ns)


When I calculate the value of DG_DL_ABS_OFFSET0 etc. ,

which value should I choose out of 1GHz,528MHz or other frequency ?


According to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014"(page 3977).

The following sentence exists.

"The delay of the delay-line would be (DG_DL_ABS_OFFSET0 / 256)* MMDC_CH0 AXI clock (fast clock)."


What is the value of  "MMDC_CH0 AXI clock(fast clock) " ?

I think it is 528MHz.

Is this correct or not ?


Likewise,what is the value of  "clock period" of "WL_DL_ABS_OFFSET0" ?


Best Regards,

Seiichi Nakano