Inverted colors on LVDS split-mode 1920x1200, imx6q on Variscite DART-Board and Innolux G170J1-LE1 display

[ralfzeuka]

Hello together,

I'd like to run a innolux display with a resolution of 1920x1200px. There is already a stable output. But the colors seems to be inverted.
black --> white

white --> black

red --> cyan

yellow --> blue

blue --> yellow

...

Is there a way to tell the video mode or the framebuffer to invert every pixel code? (not to change msb/lsb)

EDIT: The whole pixels can be inverted by changing two pins of the differential signal on a channel. In my case it was a hardware problem.

Best regards,

ralf

System:

Android: 5.0

Kernel:   3.10.35

Display:

http://www.data-modul.com/tl_files/dm/data/specification_12008329.pdf

Boot-command-line:

console=ttymxc0,115200 init=/init video=mxcfb0:dev=ldb,bpp=24,if=RGB24,fbpix=GBR24 ldb=spl0 video=mxcfb1:dev=ldb,bpp=24,if=RGB24,fbpix=RGB24 ldb=spl1 video=mxcfb2:off arm_freq=1000 fbmem=24M vmalloc=400M androidboot.console=ttymxc0 androidboot.hardware=freescale no_console_suspend androidboot.batt_poweron=good_battery androidboot.console=ttymxc0 consoleblank=0 cma=384M androidboot.selinux=disabled androidboot.dm_verity=disable androidboot.serialno=1c1bb1d4df647283

Device-Tree:   

&ldb {

    status = "okay";

    split-mode;

    lvds-channel@0 {

        fsl,data-mapping = "spwg";

        fsl,data-width = <24>;    

    primary;

        status = "okay";

        display-timings {

            native-mode = <&timing0>;

            timing0: hsd100pxn1 {

                clock-frequency = <154130000>;

                hactive = <1920>;

                vactive = <1200>;

                hback-porch = <80>;

                hfront-porch = <80>;

                vback-porch = <17>;

                vfront-porch = <18>;

                hsync-len = <13>;

                vsync-len = <13>;

                hsync-active = <0>;

                vsync-active = <0>;

                de-active    = <1>;

            };

        };

    };

    lvds-channel@1 {

        fsl,data-mapping = "spwg";

        fsl,data-width = <24>;

        status = "okay";

        display-timings {

            native-mode = <&timing1>;

            timing1: hsd100pxn1 {

                clock-frequency = <154130000>;

                hactive = <1920>;

                vactive = <1200>;

                hback-porch = <80>;

                hfront-porch = <80>;

                vback-porch = <17>;

                vfront-porch = <18>;

                hsync-len = <13>;

                vsync-len = <13>;

                hsync-active = <0>;

                vsync-active = <0>;

                de-active    = <1>;

            };

        };

    };

};

&ldb {

    lvds-channel@0 {

        crtc = "ipu1-di0";

    };

    lvds-channel@1 {

        crtc = "ipu2-di0";

    };

};

[ashleysheng]

Hi Ralf Zeuka,

I'm stuck in a display problem, and I'm think if it is possible can you provide some suggestion to me.

In our android (5.0) project, we use a KOE panel with the resolution 1920*1200. I was able to make the panel working correctly in split mode after system boots into kernel. However, the panel can't show anything during u-boot phase. Since you mentioned you got stable output for your panel, I want to know can you share your experience on how did you configure your panel in u-boot stage?
The following is my display configuration in u-boot. Can you give me some suggestions? Thanks.

struct display_info_t const displays[] = {{

.bus = -1,

.addr = 0,

.pixfmt = IPU_PIX_FMT_RGB24,

.detect = NULL,

.enable = enable_lvds,

.mode = {

.name = "KOE-XGA",

.refresh = 60,

.xres = 1920,

.yres = 1200,

.pixclock = 12762,

.left_margin = 50,

.right_margin = 65,

.upper_margin = 10,

.lower_margin = 5,

.hsync_len = 2,

.vsync_len = 2,

.sync = FB_SYNC_EXT,

.vmode = FB_VMODE_NONINTERLACED

}

static void setup_display(void)

{

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

int reg;

/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */

imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

enable_ipu_clock();

imx_setup_hdmi();

/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

reg = readl(&mxc_ccm->CCGR3);

reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

writel(reg, &mxc_ccm->CCGR3);

/* set LDB0, LDB1 clk select to 011/011 */

reg = readl(&mxc_ccm->cs2cdr);

reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

writel(reg, &mxc_ccm->cs2cdr);

reg = readl(&mxc_ccm->cscmr2);

reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;

writel(reg, &mxc_ccm->cscmr2);

reg = readl(&mxc_ccm->chsccdr);

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);

writel(reg, &mxc_ccm->chsccdr);

reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW

| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW

| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG

| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT

| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG

| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT

| IOMUXC_GPR2_SPLIT_MODE_EN_MASK

| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0

| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;

writel(reg, &iomux->gpr[2]);

reg = readl(&iomux->gpr[3]);

reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK

| IOMUXC_GPR3_LVDS1_MUX_CTL_MASK))

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);

writel(reg, &iomux->gpr[3]);

}

Best Regards,

Ashley

[b36401]

Please try to play with polarity bit in LVDS configuration.

Have a great day,

Victor

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