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HELP!!!  Last bit of Kinetis DSPI Byte Transfer is Trucated

Question asked by Myke Predko on Jan 14, 2016
Latest reply on May 31, 2016 by Diego Colombo

I have also put this question on the SDK forum, but I need to get a reply ASAP on this issue. 


I'm struggling with trying to get SD Cards working with the K22F and I'm wondering about the dspi clock.


As I mentioned in a previous question, the last bit of a dspi byte transfer is truncated as you can see in this quick and dirty screenshot:


The bottom line is the dspi sck and you can see that the "low" half of the cycle is truncated into the first bit of the next transfer.


The dspi was selected from PE with a clock speed of 375kHz with Clock cfg.4 on a FRDM-k22F board.


I'm looking around and can't find any reason of what I'm doing wrong, 375kHz is a "Possible setting" so I presume that means that the clock is divided evenly (although evidence suggests this is not the case).


Can anybody help?