About adjust the timing by CMD19 in SDR104 mode.

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About adjust the timing by CMD19 in SDR104 mode.

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keitanagashima
Senior Contributor I

Dear All,

Hello. I have questions about adjust the timing feature by CMD19 in i.MX6DQ.

uSDHC interface adjusts timing by CMD19 in case of SDR104 operation.

[Q1]

Does this adjustment execute for only all data lines?

(Does it adjust for CMD, too?)

[Q2]

When both (DATA, CMD) are adjusted,

Does "tOP" get the value which depends on each DATA/CMD line?

(When CMD and DATA signals have phase difference, does it have an influence to the tuning?)

[Q3]

Which signal does it based by this adjustment?

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

1. yes only for data lines. Ssince processor buffers and delays are made identical

for data and cmd signals, so adjustment made for data lines will wotk for cmd line too

2.>When CMD and DATA signals have phase difference, does it have an influence to the tuning?

no.

>Does "tOP" get the value which depends on each DATA/CMD line?

what is "tOP" ?

3. procedure is described in SD 3.0 Part1 Physical Layer Specification sect.4.2.4.5.

SD host send the cmd19 and set the delay value(0-127)

and the sdcard return 64 bytes data. If the data is same with

the tuning data. The delay value is valid. Execute this commmand

128 times. And calculate the longest window of the valid values.

The value in the middle of this window is the best value.

Code example can be found on:

https://github.com/linksprite/u-boot-acadia1.0-beta/blob/master/u-boot-acadia1.0-beta/patches/0372-E...

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

1. yes only for data lines. Ssince processor buffers and delays are made identical

for data and cmd signals, so adjustment made for data lines will wotk for cmd line too

2.>When CMD and DATA signals have phase difference, does it have an influence to the tuning?

no.

>Does "tOP" get the value which depends on each DATA/CMD line?

what is "tOP" ?

3. procedure is described in SD 3.0 Part1 Physical Layer Specification sect.4.2.4.5.

SD host send the cmd19 and set the delay value(0-127)

and the sdcard return 64 bytes data. If the data is same with

the tuning data. The delay value is valid. Execute this commmand

128 times. And calculate the longest window of the valid values.

The value in the middle of this window is the best value.

Code example can be found on:

https://github.com/linksprite/u-boot-acadia1.0-beta/blob/master/u-boot-acadia1.0-beta/patches/0372-E...

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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7,515 Views
keitanagashima
Senior Contributor I

Dear Igor,

Hello.

Thank you for your reply.

> 1. yes only for data lines. Since processor buffers and delays are made identical

> for data and cmd signals, so adjustment made for data lines will work for cmd line too

I understood that It adjust for data and cmd lines.

>> 2

>>Does "tOP" get the value which depends on each DATA/CMD line?

> what is "tOP" ?

Please refer to attached file.

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

>Does "tOP" get the value which depends on each DATA/CMD line?

No.

Best regards

igor

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keitanagashima
Senior Contributor I

Dear Igor,

Hello. Thank you for your quick reply.

Sorry, I mistook my question.

Does "tOP" get a different value which depends on each DATA/CMD line?

(Ex, DATA1 and DATA2 lines got different tOP value.)

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

no, "tOP" does not get a different value

Best regards

igor

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7,515 Views
keitanagashima
Senior Contributor I

Dear Igor,

Hello. Thank you for your reply.

Sorry for many questions.

Let me confirm the AC spec.

[Q1] (i.MX6 read the data from SD)

When the automatic adjustment execute by CMD19, is there a AC specification in the phase difference between CMD, DATA[3:0] and CLK?

I think that the spec doesn't exist because the timing was tuned by auto adjustment.

[Q2]

CMD and Clock (SDR104) communicate with the SD card before the auto adjustment execute by CMD19.

Is it necessary to care the AC timing between CMD and CLK before auto adjustment?

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

1. you are right

2. sampling point should have sufficient timings  to recognize commands

before CMD19. If it is not sufficient, starting point can be determined experimentally

using section 67.5.3.2.4 "DLL (Delay Line) in Read Path"  RM.

Best regards

igor

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keitanagashima
Senior Contributor I

Dear Igor,

Hello. Thank you for your reply.

>sampling point should have sufficient timing

Does this mean we should care the "SD5 uSDHC Output Delay tOD" parameter from Table 56. SDR50/SDR104 Interface Timing Specification in IMX6DQAEC(Rev.4)?

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

I think you are right: SD5 should be cared.

CMD19 timings are for uSDHC input timings, while SD5 - uSDHC Output

timings.

Best regards

igor

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keitanagashima
Senior Contributor I

Dear Igor,

Hello. Sorry, let me confirm the below thing again.

I understood that the ODW(Card Output Data Windom) spec only exist and Setup/Hold time doesn't exist because auto adjustment between uSDHC and SD card.

> 2. sampling point should have sufficient timings to recognize commands

> before CMD19. If it is not sufficient, starting point can be determined experimentally

> using section 67.5.3.2.4 "DLL (Delay Line) in Read Path"  RM.

Before auto-adjusting, only the CMD signal communicates at the speed of SDR104.

At this time, can i.MX6 read CMD surely? (i.e. Is it necessary to care Clock and CMD?)

I couldn't understand the " sufficient timing".

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

" sufficient timing" should be provided by appropriate

board layout defined in i.MX6 System Development User’s Guide (rev.1, 6/2013)

and ibis modelling, that is following this board design flow i.MX6 will read CMD surely.

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards

igor

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keitanagashima
Senior Contributor I

Dear Igor,

Hello. Thank you for your prompt reply.

I couldn't find the board layout for uSDHC defined in Development User’s Guide.

Should one care the only ibis modelling?

Does i.MX6 has AC timing spec (sufficient timing) at the uSDHC read operation between clock and CMD?

Best Regards,

Keita

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igorpadykov
NXP Employee
NXP Employee

Hi Keita

for SD interface layout recommendations are given in

sect.3.5.8 High speed signal routing recommendations

>Does i.MX6 has AC timing spec (sufficient timing) at the uSDHC read operation between clock and CMD?

yes, however when processor and sd card are soldered on board

one needs to follows layout recommendations and performs ibis modelling to

account for additional delays introduced by board traces

Best regards

igor

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