AnsweredAssumed Answered

Troubleshooting DDR2 RAM problems

Question asked by Adam Crowder on Jun 2, 2015
Latest reply on Nov 18, 2015 by TomE

I have a prototype design on my desk which occasionally (10 - 20% of the time) fails to initialize its DDR RAM on power-up.

 

Our boot code, as a matter of its power-up sequence, relies on the MCF5441x internal SRAM for its variable and stack space, in order to be able to bring up the DDR2 RAM and test it without worries.

 

The first test run by our "Fast RAM Test" is to write the first longword in RAM with a value of 1, then read it back.  Then same test with same memory location, with a value of 2, etc., shifting the bit leftward each time.

 

When the module fails on boot, the very first RAM test fails.  Now, when the test fails, the code displays its error on the LCD then enters a tight loop until the [external] watchdog chip asserts the hardware /RESET line.  The RAM always works correctly on the 2nd boot.

 

Earlier today, I added a loop at the end of my DRAM init function to wait for the "DRAM initialization complete" bit in "DDR_CR27".  It appears to set in every case, even when the RAM fails to test later.

 

void hardware_init_sdram( void) {

//#Select DDR 2x clock to PLL VCO

(*(vuint16*)(0xEC09001A)) = 0xa002;         // MISCCR2 P.10-3  10-11

 

//#Enable clocks for DDR Controller

(*(vuint8*)(0xFC04002D)) = 0x2E;      // PPMCR0 P.9-1, 9-4.  Enable clock x2E (46), the SDRAM.  Already done above.

 

//#Configure DDR2 deive strength 1.8V

//(*(vuint8*)(0xEC094060)) = 0x01;  // MSCR_SDRAMC p.15-13, 15-24 Full strength

(*(vuint8*)(0xEC094060)) = 0x00;  // MSCR_SDRAMC p.15-13, 15-24 Half strength

 

//   Wait( 100);  // Uncomment this and ALL HELL BREAKS LOOSE.  (don't do it)

 

// Following was suggested by Rocky to try to thwart the occasional RAM-fail-caused

// double-boot.  It *might* have helped, but did not cure:

  FastTimer( 100); // Already "tuned" because LCD is lit up.

 

  (*(vuint32*)(0xFC0B8180)) = 0x00000000; // RCR

  (*(vuint32*)(0xFC0B8180)) = 0x40000000; // RCR

  (*(vuint32*)(0xFC0B81AC)) = 0x01030203; // PADCR

 

  (*(vuint32*)(0xFC0B8000)) = 0x01010101; // CR00

  (*(vuint32*)(0xFC0B8004)) = 0x00000101; // CR01

  (*(vuint32*)(0xFC0B8008)) = 0x01010100; // CR02

  (*(vuint32*)(0xFC0B800C)) = 0x01010000; // CR03

  (*(vuint32*)(0xFC0B8010)) = 0x00010101; // CR04

  (*(vuint32*)(0xFC0B8018)) = 0x00010100; // CR06

  (*(vuint32*)(0xFC0B801C)) = 0x00000001; // CR07

  (*(vuint32*)(0xFC0B8020)) = 0x01000001; // CR08

  (*(vuint32*)(0xFC0B8024)) = 0x00000100; // CR09

  (*(vuint32*)(0xFC0B8028)) = 0x00010001; // CR10

  (*(vuint32*)(0xFC0B802C)) = 0x00000200; // CR11

  (*(vuint32*)(0xFC0B8030)) = 0x01000002; // CR12

  (*(vuint32*)(0xFC0B8034)) = 0x00000000; // CR13 *

  (*(vuint32*)(0xFC0B8038)) = 0x00000100; // CR14

  (*(vuint32*)(0xFC0B803C)) = 0x02000100; // CR15

  (*(vuint32*)(0xFC0B8040)) = 0x02000407; // CR16

  (*(vuint32*)(0xFC0B8044)) = 0x02030007; // CR17

  (*(vuint32*)(0xFC0B8048)) = 0x02000100; // CR18

  (*(vuint32*)(0xFC0B804C)) = 0x0A030203; // CR19

  (*(vuint32*)(0xFC0B8050)) = 0x00020708; // CR20

  (*(vuint32*)(0xFC0B8054)) = 0x00050008; // CR21

  (*(vuint32*)(0xFC0B8058)) = 0x04030002; // CR22

  (*(vuint32*)(0xFC0B805C)) = 0x00000004; // CR23

  (*(vuint32*)(0xFC0B8060)) = 0x020A0000; // CR24

  (*(vuint32*)(0xFC0B8064)) = 0x0c00000e; // CR25

  (*(vuint32*)(0xFC0B8068)) = 0x00002004; // CR26

  (*(vuint32*)(0xFC0B806C)) = 0x00000000; // CR27 *

  (*(vuint32*)(0xFC0B8070)) = 0x00100010; // CR28

  (*(vuint32*)(0xFC0B8074)) = 0x00100010; // CR29

  (*(vuint32*)(0xFC0B8078)) = 0x00000000; // CR30 *

  (*(vuint32*)(0xFC0B807C)) = 0x07990000; // CR31

 

  (*(vuint32*)(0xFC0B80A0)) = 0x00000000; // CR40

  (*(vuint32*)(0xFC0B80A4)) = 0x00000064; // CR41

  (*(vuint32*)(0xFC0B80A8)) = 0x44520002; // CR42

  (*(vuint32*)(0xFC0B80AC)) = 0x00C80023; // CR43

 

  (*(vuint32*)(0xFC0B80B4)) = 0x0000c350; // CR45

 

  (*(vuint32*)(0xFC0B80E0)) = 0x04000000; // CR56

  (*(vuint32*)(0xFC0B80E4)) = 0x03000304; // CR57

  (*(vuint32*)(0xFC0B80E8)) = 0x40040000; // CR58

  (*(vuint32*)(0xFC0B80EC)) = 0xC0004004; // CR59

  (*(vuint32*)(0xFC0B80F0)) = 0x0642C000; // CR60

  (*(vuint32*)(0xFC0B80F4)) = 0x00000642; // CR61

 

//    asm( "    .balignw    4, 0x51FC"); // Pad to align with TPF (TRAPF)

  (*(vuint32*)(0xFC0B8024)) = 0x01000100;

 

  while( !(MCF_DDR_CR27 & MCF_DDR_CR27_INTSTATUS_DRAM_INIT ) )

    Wait( 1);

  Wait(100);

}

 

Any suggestions for testing would be appreciated!

 

--Adam

Outcomes